Community Newsletter: September 2019


IN THIS ISSUE:

 

Message from the Chair

Lu Dai, Accellera Systems Initiative ChairIt has been a busy few months at Accellera. If you weren’t able to join us at the 56th Design Automation Conference (DAC), our lunch panel on IP Security issues drew a standing-room-only crowd eager to hear what our panel of experts had to say. It was a very engaging and thought-provoking discussion among panelists and audience members that is sure to continue in further conversations throughout the industry.

With summer coming to a close, we have had our sights set on our upcoming events in India and Europe. DVCon India returns as a two-day conference in Bangalore at the end of September. The revamped program will focus on user-driven content and will have in-depth technical tutorials presented by experts in their fields.

Now in its sixth year, DVCon Europe will be held in Munich, Germany and will be co-located again this year with SystemC Evolution Day at the end of October. Collaboration at these events has been a key factor in the development and evolution of new efforts within Accellera. Multiple discussions at DVCon Europe last year resulted in the creation of the UVM-AMS Proposed Working Group. We look forward to your attendance and participation in our upcoming events.

We’ve also been making good progress on our standardization efforts:

  • The Portable Stimulus Working Group has been very hard at work on a 1.1 update that is targeted for release in the first half of 2020.
  • As a result of a special request from the IEEE, the IP-XACT Working Group is meeting regularly to update IEEE 1685-2014.
  • With the tremendous momentum and interest received during the DAC lunch panel, the IPSA Working Group continues to make great progress on both the tool and attack database fronts.
  • Although still a Proposed Working Group, UVM-AMS has already received significant contributions from industry veterans demonstrating great interest in a potential standard in this area.

If you aren’t currently an Accellera member, we encourage you to join and participate in our standardization efforts. It is an opportunity to guide and contribute to working groups of interest, participate in forum discussions, brainstorm new ideas, and have an impact in standards that help our industry. We have established a new public repository that is initially for SystemC reference implementation material, but will grow to include more. The repository will make it even easier to access our material.

Great engineers don’t complain, they provide proposals for change. Join Accellera and make your voice heard. We welcome your ideas, your leadership, and your efforts to help us continue to evolve and change for the better.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

DVCon India 2019

DVCon India 2019DVCon India will be held September 25-26 at the Radisson Blu Bengaluru in Bangalore, India. Since its inception in 2014, DVCon India has become a well-established conference developed for users by the local design and verification community.

The first day of the conference and exhibition will have two keynotes: “The Evolution of Static Verification,” presented by Sridhar Seshadri, Synopsys, Inc. and “Driving Digitalization with a Boundary Free Innovation Platform,” presented by Stefan Jockusch, Siemens PLM Software, Inc. There will also be two panels: “Can Designs be Signed Off with Formal Verification Alone?” moderated by Ashok Kumar Natarajan, Intel Corp. and “AI/ML in Design and Verification- Problems/Solutions, Challenges and Effectiveness,” moderated by Sidhartha Mohanty, Intel Corp. Four short workshops and six tutorials round out opening day. Day two will offer attendees 12 regular sessions to choose from, as well as a poster session with 15 poster presentations.

The technical program covers a broad range of topics including Portable Stimulus, machine learning, RISC-V, and much more. There will be many opportunities for attendees to network with their peers and experts in the industry during the tea breaks and the exhibition held both days.

“For 2019, our ambition remains unchanged: to offer a compelling event where technical experts active in system-level design and verification can interact, share best practices, and learn the latest design and verification methodologies, languages, and standards,” stated Sanjay Muchini, DVCon India 2019 General Chair.

For the more information on DVCon India 2019 and to view the complete technical program, visit the DVCon India website.

 

DVCon Europe 2019

DVCon Europe 2019The sixth annual DVCon Europe will be held October 29-30 at the Holiday Inn Munich City Centre in Munich, Germany. The conference and exhibition opens with a keynote presented by Lars Reger, NXP Semiconductors titled, “Safe Computing at the Edge” that will discuss edge computing and explore the challenges on the route to an ever smarter on-demand world. The day continues with 16 tutorials covering topics such as IP-XACT, RISC-V compliance and verification techniques, functional safety verification for ISO-26262-compliant designs, and next-generation system design and verification for transportation.

Day two opens with a keynote address, “Enabling Technologies and the Future of Networks,” by Preeti Nagarajan, Ericsson that will discuss the dilemma of quicker innovation needed in enabling technologies to support complex systems in a consolidating and geopolitically polarized industry landscape. A panel, “Imagining How Artificial Intelligence Could Reshape the Verification Landscape,” follows that will have chip design verification experts explore various scenarios to determine if the verification landscape needs to be modified. There will also be 12 sessions on day two covering a variety of topics including Portable Stimulus, SystemC, RISC-V, UVM, and emulation. A second panel, “Applying the New Breed of Automotive Specific, Next-Generation Verification Technologies,” will examine the various techniques and their use today in leading automotive flows, and will consider the most effective approaches.

There will be an exhibition and reception both days, giving attendees time to connect with colleagues and learn about the latest tools and technologies to help in their day-to-day jobs.

For more information on DVCon Europe 2019 and the complete technical program, visit the DVCon Europe website.

 

SystemC Evolution Day 2019

SystemC Evolution Day 2019SystemC Evolution Day will be co-located with DVCon Europe again this year and will follow the conference on October 31 at the Holiday Inn Munich City Centre. In its fourth year, it is a full-day technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for inclusion in Accellera/IEEE standards.

In a recent blog, “SystemC Evolution Day 2019: Driving the Future of SystemC,” Philipp Hartmann, Accellera SystemC Language Working Group Chair, stated “The organization team has announced a full-day program, covering a wide range of industry-relevant topics contributed by different user companies. The result is a packed agenda organized along three different sessions with focus areas of simulation technology, transaction-level modeling, and model creation.”

Oliver Bell, Chair of SystemC Evolution Day, covers its history in a blog, “The Future is Embedded! Join SystemC Evolution Day 2019.”

For more information on SystemC Evolution Day and the complete program, visit the Accellera SystemC Evolution Day web page.

The presentations from SystemC Evolution Day 2018 are available for download.

 

DVCon U.S. 2020

DVCon U.S. 2020DVCon U.S. 2020 will be held March 2-5, 2020 at the DoubleTree Hotel in San Jose, California.
 
“Now in its 32nd year, DVCon U.S. has continued to evolve its program each year with the growing needs of our attendees, making it the industry’s must-attend conference,” stated Aparna Dey, DVCon U.S. 2020 General Chair.  “Our goal is to provide a platform where design and verification engineers and vendors can come together to discuss their challenges and solutions. DVCon continues to be an opportunity for collaboration among peers. Our hope is that they gain practical knowledge that they can apply immediately in their day-to-day jobs. The DVCon U.S. steering committee will be working hard to select the best of the best submissions to create a highly technical and beneficial program. We welcome submissions that address traditional design and verification topics, as well as those that include machine learning, intelligent systems, industrial, automotive safety, aerospace, cloud data center, IP, and security.”

The deadline for tutorial, panel and short workshop proposals is September 24, 2019.

 

IEEE Get Program Crosses 100,000 Downloads!

For almost a decade Accellera has worked with the IEEE Standards Association to sponsor the IEEE GET Program. Through the Accellera-sponsored program, seven standards are currently made available to users free of charge. The IEEE GET Program has resulted in over 100,000 downloads since it was established in 2010, giving engineers and chip designers worldwide no-cost access to electronic design and verification standards. For more information on available standards, see the Accellera downloads.

 

Lu Dai Discusses the Value of Accellera Membership During an Interview with EDA Café

In a recent interview with Sanjay Gangal, president of IBSystems, Accellera Chair Lu Dai explains the value of Accellera membership for both user and vendor companies. During the interview at the 56th Design Automation Conference in Las Vegas, Lu describes how standards are initiated within the organization as well as how companies can get involved and contribute to drive new standards development. He also discusses Accellera’s latest standards effort, the IP Security Assurance Working Group, as well as the UVM-AMS Proposed Working Group gauging industry interest in moving forward with developing a new standard.

View the interview >

 

Working Group Highlight

IP Security Panel at DAC Draws Crowd Eager for Answers

IP Security Lunch Panel at DAC

Four experts in IP security came together at the Design Automation Conference in Las Vegas, NV earlier this year to discuss some of the fears regarding security and to discuss what the future of security-aware design and verification might hold. The Accellera-sponsored lunch panel was moderated by Adam Sherer, IPSA Working Group Secretary and included: Lei Poo, Analog Devices, Inc.; Brent Sherman, Intel and IP Security Assurance (IPSA) Working Group Chair; Andrew Dauman, Tortuga Logic; and Serge Leef, DARPA. An overview of the panel discussion can be found in a two-part blog posted by Cadence.

IP Security Assurance Working Group Whitepaper Now Available

A whitepaper is now available from the IP Security Assurance (IPSA) Working Group that describes Accellera’s initial proposal to address the industry’s security concerns involving IP integration. Since integrators typically treat IP as a “black box,” vulnerabilities may inadvertently be inserted into an SoC/ASIC. The whitepaper details the objectives of the IPSA standard and its approach, along with real-case examples highlighting the methodology.

View/download the whitepaper >

The IPSA Working Group is seeking input from the community on the whitepaper. To provide feedback or ask questions about the emerging IPSA standard, please use the newly established IPSA Community Forum.

 

In the News

Public Repository Now Available

Accellera recently announced the availability of a public repository for supplemental material related to its standards. The Accellera public repository will be hosted at GitHub and will initially contain the SystemC reference implementation. It will be available to the community to clone or fork for their specific use. The public repository will also contain the latest bug fixes. Alongside the new public repository, the Accellera private repository remains available for Accellera member companies, containing the latest enhancements and new features. Accellera will continue to release its supplemental material via the Accellera download pages and will update the public repositories at these release dates.

A press release is available for more information.

 

SystemC Tutorial from DVCon U.S. 2019 Now Available

SystemC

Consisting of five parts, the tutorial “SystemC: Focusing on High-Level Synthesis and Functional Coverage for SystemC” was presented at DVCon U.S. 2019 by members of the SystemC Working Groups. It provides an overview on High Level Synthesis (HLS) with a discussion on data types and model structure as well as lessons learned. It also includes Functional Coverage for SystemC and a brief update on the Accellera SystemC Working Group.

Registration is required to view the tutorial.

 

 

 

2019 Global Sponsors

CadenceMentor GraphicsSynopsys

Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.

 

Copyright 2019 Accellera Systems Initiative