Community Newsletter: December 2019
IN THIS ISSUE:
- Message from the Chair
A very productive year filled with standards development and conferences around the globe
- Working Group Highlight
Interview with UVM-AMS Working Group Chair Patrick Lynch
- Looking Forward to DVCon U.S. 2020
General Chair Aparna Dey welcomes you to the 32nd annual DVCon; the program is available and registration is open
- Looking Forward to DVCon China 2020
General Chair Bin Liu welcomes you to the 4th annual DVCon China
- DVCon Europe 2019 Wrap-up
6th annual conference enjoys 20% growth
- SystemC Evolution Day 2019 Wrap-up
Chair Oliver Bell gives highlights of the day
- DVCon India 2019 Wrap-up
Nearly 500 attendees gather to learn the latest in design and verification
- Accellera in the News
Proposed Working Group to address Functional Safety Established
Accellera Forms UVM-AMS Working Group
Accellera Media Coverage
- New Material Available in 2019
Tutorials from DVCon U.S., a whitepaper on IP Security, and more!
Another exciting and very busy year at Accellera is coming to an end, and as I look back, we have much to be proud of.
Our DVCon conferences throughout the globe reached nearly 2,000 attendees with thought-provoking technical presentations and many engaging discussions. DVCon India was back and even better this year with excellent attendance from both local and multinational companies. DVCon Europe completed its 6th successful conference and exhibition in Munich, Germany. SystemC Evolution day generated a great deal of participation and brought the community and working groups close together to advance SystemC standards. In addition, our flagship conference DVCon U.S., as well as DVCon China, had excellent participation and attendance earlier this year.
We announced the formation of the Functional Safety Proposed Working Group to address the needs of the autonomous driving market, as well as the UVM-AMS Working Group, recently approved by the Board of Directors. Although both are very new, we’re are already receiving excellent contributions from participants. The IP Security Assurance Working Group, formed just over a year ago, has published its first whitepaper with contributions and examples from experts across the industry. The working group continues to solicit feedback from the community and is diligently working to integrate the suggestions.
The IP-XACT Working Group met recently in Paris and is moving forward with updates for the next revision of the standard. They are working on both implementations as well as validations. Development of Portable Stimulus 1.1 is well-underway; requirements have been finalized, and the implementation is making great progress. We eagerly await the upcoming releases from both working groups.
Earlier this year we also established a public repository for supplemental material related to our standards.
DVCon U.S. 2020 is coming soon after the New Year, and we hope you will join us for the 32nd annual conference in San Jose, California.
As always, we encourage you to bring your questions and suggestions to our community portal. Our working group leadership values all input and reviews it carefully.
From all of us at Accellera, we wish you a wonderful holiday season and Happy New Year.
Lu Dai, Accellera Systems Initiative Chair
Q&A with UVM-AMS Working Group Chair Patrick Lynch
Q: What is the focus of the new working group?
A: The charter of the new working group is to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems.
Q: What value will the UVM-AMS standard bring to the community?
A: The UVM-AMS WG envisions the availability of an industry-agreed analog/mixed-signal verification methodology based on its planned UVM-AMS standard. This will encourage support by tool and IP providers, offering ready-to-use analog/mixed-signal verification IP that can be integrated easily into a UVM-AMS testbench. It will raise the productivity and quality of analog/mixed-signal verification across projects and applications, thanks to the reuse of proven verification components and stimuli.
Q: What is the working group activity in the first 6 to 12 months?
A: We will initially focus on consolidating the industry requirements of UVM-AMS and develop a whitepaper that will help define the scope of the standardization effort. This whitepaper will be shared with the AMS verification community to benchmark the ideas of the working group with the expectations of the industry.
Q: What will be defined in the UVM-AMS standard?
A: Similar to UVM, the UVM-AMS standard will define a set of application programming interfaces (APIs) to enable the development of modular, scalable, and reusable AMS verification components and testbenches. To this purpose, the standard will define the language constructs and execution semantics supporting an AMS verification methodology based on simulation techniques.
Q: Will the working group develop a reference implementation?
A: The primary focus of the working group is to develop the UVM-AMS standard. To assure that the standard can be implemented, the development of a reference implementation is considered, but dependent on potential contributions of the Accellera member companies active in the working group. We encourage member companies to donate their prototypes and examples, which could serve as a starting point for the development of such a reference implementation.
Q: What will be the foundation language for UVM-AMS?
A: There are various languages used for AMS verification, such as Verilog-AMS, SystemVerilog, and also SystemC-AMS. The aim is to define a standard API that is language-agnostic to enable the creation of a reference implementation in any of these languages.
Q: My EDA tool provider offers AMS extensions for UVM. Is this compatible with the planned UVM-AMS standard?
A: As UVM-AMS is not defined as a standard yet, existing EDA solutions are independent from this standardization initiative. We encourage EDA solution providers to participate in the UVM-AMS Working Group and share their experiences so industry usage and methodologies can be incorporated into this future standard.
Q: I currently use Interface Verification IP which only supports digital signals. Should I replace them with AMS Verification IP?
A: The objective of the UVM-AMS standard is to introduce dedicated capabilities that enable making AMS extensions to digital-centric verification IP. As UVM offers the foundation technology, we could benefit from using testbench configuration, factory-based component overrides, and virtual interfaces to seamlessly insert AMS components, signals, and analysis in an existing digital-centric verification IP. Obviously, this extension heavily depends on the flexibility and configurability offered in the digital VIP itself.
Q: Will UVM-AMS support multi-language verification?
A: The main focus of UVM-AMS is to standardize the API to drive and monitor analog/mixed-signal nets within UVM, including stimulus, scoreboarding, and analysis. The multi-language aspects are out-of-scope for the UVM-AMS Working Group. There is another Accellera working group active with the objective to develop a standard for multi-language verification.
Q: Will the UVM-AMS Working Group develop specific AMS verification IP?
A: The primary objective of the UVM-AMS Working Group is to develop a standard that forms the framework to develop AMS verification components or testbenches. As such, the working group itself will not develop these elements. The internal functionality to drive, monitor, or analyze AMS signals should be developed by the verification team. However, to explain how to create an AMS verification IP or testbenches to the AMS verification community, it is expected that there will be basic examples available as part of the deployment of the UVM-AMS standard.
For more information on the UVM-AMS Working Group, visit the working group page.
March 2-5, 2020
Message from DVCon U.S. General Chair Aparna Dey
I am pleased to welcome you to the DVCon U.S. 2020 conference and exhibition! This year, DVCon promises to provide the attendees with outstanding technical sessions and discussions on many hot topics, practical learning, networking, and an opportunity to preview the latest industry design and verification tools and services from the best in the industry. We are proud of continuing our tradition of providing an annual technical forum that serves the needs of the design and verification community, organized by dedicated volunteers from the community itself.
Now in its 32nd year, DVCon U.S. has established itself as the must-attend industry- and user-focused conference for practicing design and verification engineers, EDA developers, and design managers, focusing on design and verification of electronic systems and integrated circuits. We are proud that this conference attracts wide participation from the smaller to the larger companies in the industry in both the full program and exhibition. We are also pleased that the success of DVCon U.S. and its format has spawned successful local DVCon events worldwide in Europe, China, and India to meet the local needs of these regions.
Our 4-day program includes many key design and verification topics including Formal Verification, Portable Stimulus, IP Security, Intelligent System Design, AI and ML-focused Verification, 5G Verification, UVM Strategies, Power-Aware Design, Hybrid Verification, and more. The event provides an opportunity to discuss challenges and solutions that can be beneficial in current and upcoming projects as electronic designs and verification complexities and challenges continue to increase exponentially. Attendees will find each of these areas addressed in the conference’s sessions, panels, posters, tutorials, and short workshops with an emphasis on solutions to engineers’ real-world problems.
We are pleased to offer an in-depth technical program this year. We received over 160 outstanding submissions for papers, panels, tutorials, and short workshops from the best technical minds and organizations in the industry. Our focus on the users of Accellera standard EDA languages, tools, and methodologies continues to be a DVCon 2020 hallmark. Attendees can expect to learn about both practical solutions to their pressing problems and preview the technologies that will affect them in the near future.
I am pleased to present the work of the DVCon Steering Committee and Technical Program Committee, who have put together an excellent 2020 program with the support of our conference management specialists, MP Associates.
Highlights of the conference include:
- Accellera Day: On Monday, March 2, our conference sponsor, Accellera Systems Initiative, kicks off DVCon U.S. with Accellera Day. We’ll have a full-morning Accellera tutorial on Portable Stimulus and the standard’s latest version updates as well as two Accellera short workshops in the afternoon on SystemC case studies and the IP Security Assurance standard presented by Accellera standards working group members. We’ll also have four sponsored short workshops in the afternoon presented by design verification industry members covering topics such as Portable Stimulus deployment, SOC methodology, and UVM testbenches.
- Keynote: This year’s keynote, “Artificial Intelligence for Design Automation,” will be given by Dr. Anirudh Devgan, president of Cadence Design Systems, Inc. Dr. Devgan’s talk will review the latest trends in artificial intelligence and machine learning and their impact on the EDA industry. He will examine how deep learning will chart a path beyond current practices, moving toward intelligent system design for an AI-enabled future.
- Technical papers and posters: Technical Program Chair, Vanessa Cooper, and Poster Chair, John Dickols, have organized an excellent technical program on Tuesday and Wednesday with 13 sessions that include 42 papers and 23 posters. We are very grateful for the outstanding submissions and the work done by the technical program committee volunteers to review the submissions and encourage the community to keep submitting. There are so many good choices that you will want to go through the program and review it thoroughly as you plan each day. There is something for everyone in this broad, in-depth technical program. With so many interesting options, we look forward to your votes for the Best Paper and Best Poster awards after the last program session on Wednesday.
- Tutorials and Short Workshops: Ambar Sarkar, Tutorial and Short Workshop Chair, has put together an outstanding selection of tutorials and short workshops for Monday and Thursday. The short workshops are very popular and are intended to give more organizations, mostly smaller companies, greater opportunity to participate in the program and give attendees more variety in shorter educational and learning sessions. We have eight sponsored short workshops in this year’s program—four on Monday and four on Thursday—covering a wide variety of topics.
In addition to the Monday's opening Accellera tutorial on Portable Stimulus, we will have three sponsored tutorials on Thursday with topics covering: Deploying VCS on Cloud for faster time to market and higher quality verification; Design and Verification of an ML based SoC using a software-driven system design approach; and Next Generation Verification for the era of AI, ML and 5G.
- Panels: Tom Fitzpatrick, Panel Chair, has organized two excellent panel sessions. The first panel, “New Chip Designs Create Tidal Wave of Change,” will address the need for a more thorough verification methodology as complexity converges with open source initiatives such as RISC-V. The second panel, “Predicting the Verification Flow of the Future,” will focus on what’s straining today’s verification environment and what might be needed to support future applications. Both panels will provide some interesting perspectives for attendees to consider and also provide an opportunity to ask their own thought-provoking questions.
- Exhibits: The exhibition continues to be one of the most sought-after gathering spaces among attendees to talk with exhibitors to learn the latest information on their products, share new information among peers, and enjoy the evening networking receptions. As of this writing, the exhibit floor is nearly sold out. We have a few spaces left, but expect a full house of more than 30 when the conference begins.
My sincere thanks to our program sponsor, Accellera Systems Initiative, industry sponsors, steering committee volunteers, technical program committee volunteers, past chairs, and MP Associates staff who have worked hard to put together a program that makes DVCon “the” conference for design and verification engineers.
I sincerely look forward to seeing you in March in San Jose, CA at DVCon U.S. 2020!
DVCon U.S. 2020 General Chair
For more on DVCon and its benefits to practicing chip design and verification engineers, read John Blyler’s blog in Chip Estimate on the success of DVCon U.S. 2019 and the global impact of the conference and exhibition.
April 15, 2020
Message from DVCon China General Chair Bin Liu
I am honored to be the chair of the 4th annual DVCon China. Together with the members of the organizing committee we will provide IC industry engineers from all over the country with a platform for technical exchanges.
The DVCon China 2019 conference was very successful. We received more papers than before, and we received more attention and recognition from the industry. We hope to inject this successful conference experience into the preparation work for the conference next year.
As new products appear in the IC market, we have received more diversified solutions in chip verification. For example, testbench automation and test vector automation solutions are improving verification efficiency, and the coverage consistency requirement also makes the coverage integration of the formal verification and simulation faster.
However, we find that the complexity and the efficiency gap of verification are still expanding. We are introducing new tools and methods to make up for these gaps, but in addition to engineers needing to learn to master new tools and methods, we are also considering how to make new solutions improve the efficiency of verification and no longer bring new workload to engineers.
As a result, we have introduced the Portable Stimulus standard that is designed to describe more abstract operations based on existing system-level UVM and C tests, and then enable test reuse at different stages of development. Meanwhile, we are also discovering more value in formal verification, allowing them to perform more reliable and efficient verification than simulation in some scenarios.
Faced with so many different tools and methods, the verification engineer needs to be like a brave and wise general: choose the right solution in the intense project execution, and then report the results of the different camps together. The ability of the verification engineer is constantly extending along with the size of the chip.
Even if a verification engineer is becoming more proficient in the project and has raised many new challenges, we still need to grasp the essence of things, look for common and customized verification solutions, and which are positive for improving verification efficiency. These bright points in our daily work will also become shining stars at the annual DVCon conference, which will become a roadmap for guiding verification engineers.
I am very willing to hang up the stars with the friends of the technical committee of this conference, and I hope more new verification schemes can become these stars.
We will meet again in Shanghai in April, friends!
DVCon China 2020 General Chair
The 6th annual DVCon Europe continued this year with strong growth in attendance and an expanded program. Registration was up 20% with attendees from 111 different companies in 32 countries. The number of exhibitors also increased this year to 27 from 22 last year.
“We expanded our scope this year to include embedded software, which proved very popular,” said Joachim Geishauser, DVCon Europe General Chair. “We’ve already received good feedback on our tutorials covering software development for safety/security critical systems and autonomous flying, and we anticipate even greater focus on software next year.”
Forward-looking keynotes were presented on each day of the conference with excellent attendance. The first, from Lars Reger of NXP Semiconductor and titled “Safe Computing at the Edge,” explored how to cope with the demanding computation needs in applications such as fully autonomous cars. The second keynote, “Enabling Technologies and the Future of Networks,” was presented by Preeti Nagarajan from Ericsson and it focused on the transformation to 5G.
The award for Best Paper went to a team of engineers from Cadence Design Systems, Texas Instruments, Ben Gurion University and Bengal Engineering and Science University, for their paper titled “5.2 Portable Stimuli Over UVM, Using Portable Stimuli in HW Verification Flow.”
Save the Date! DVCon Europe 2020 will be held at the Holiday Inn in Munich, Germany on October 27 and 28, 2020. SystemC Evolution Day 2020 will be co-located again with DVCon Europe and will be held on October 29.
Co-located with DVCon Europe, the 4th SystemC Evolution Day took place on October 31, 2019. This was a very special edition, not only because of Halloween, but because of the almost 70 System-level Modeling experts from across the world who participated. This full-day technical workshop focused on the evolution of SystemC standards to advance the SystemC ecosystem.
SystemC Evolution Day started with an Accellera standardization update highlighting the developments in the various SystemC working groups. This was followed by an inspiring opening talk by Martin Barnasconi, NXP, exploring the integration opportunities and challenges of the SystemC and Digital Twin ecosystem. Nine interactive technical presentations were held during the day, addressing current and future SystemC standardization topics. Many presentations proposed features for inclusion in the Accellera/IEEE standard.
The other presentations highlighted progress and challenges in simulation and kernel technology, covering topics such as parallel SystemC simulation, synchronization of multiple simulators, and improvements for tracing. In addition, model interoperability and transaction-level modeling (TLM) were addressed including TLM extensions for buses, generic payload, and clock interfaces. Further topic areas covered model creation, high-level synthesis, and model metrics, with presentations on model introspection, advanced assertion checking, and metrics to assess model correctness and completeness. One of the highlights of this workshop was the presentation on “Pushing the Limits of Standard-Compliant Parallel SystemC Simulation.” Professor Doemer from the University of California compared the progress made since his presentation during the first SystemC Evolution Day in 2016.
Feedback about the event, from both audience and presenters, was very positive. The SystemC Evolution Day organizing committee would like to extend many thanks to all of the authors and presenters from NXP, Intel, University of California, GreenSoCs, Circuitsutra, Bosch, and Ericsson. The quality of talks was extremely high. Thanks are also due to the organization team for their dedication to a high quality program and to the working group chairs for capturing the technical meeting minutes. The intention now is that the ideas captured during the day will be driven forward into the SystemC working groups.
The presentations from SystemC Evolution Day 2019 are available for download.
Mark your calendar: SystemC Evolution Day 2020 will be co-located again with DVCon Europe and will be held on October 29 at the Holiday Inn in Munich, Germany.
DVCon India welcomed almost 500 attendees to its conference and exhibition in Bangalore. Participants in the September conference came from 65 different companies and six different countries. The keynote, tutorial, panel, poster, and short workshop sessions were each very well-attended, with many tea breaks for attendees to interact with their peers and experts in the industry. Sessions focused on a broad range of topics including machine learning, formal verification, verification of RISC-V cores, and Portable Stimulus.
Prateek Chandra, Leily Zafari, and Boyko Traykov of Infineon Technologies won Best Paper honors for their paper titled “Automatic Generation of Infineon Microcontroller Product Configurations.”
The award for Best Poster went to Vineet Tanwar, Chirag Kedia, and Rahul Gupta of Qualcomm India Private Limited for their poster titled “SoC Verification Enablement Using HM Model.”
DVCon India 2020 will be held in September of next year. Stay tuned for more details coming soon!
Proposed Working Group Established to Address Functional Safety
The Functional Safety Proposed Working Group (PWG) will focus on a standard to enable tool interoperability between Failure Modes, Effects, and Diagnostic Analysis (FMEDA) for functional safety and the design and verification flow of electronic circuits and systems.
“The EDA industry is already developing tools to perform functional safety analysis ,and this initiative aims at improving interoperability to capture, propagate, and trace the safety intent and optimizations through an EDA solution and across FMEDA tools,” stated Martin Barnasconi, Accellera Technical Committee Chair. “We invite companies active in this domain to share their best practices, requirements, and expectations on what a functional safety standard should encompass.”
The first meeting will be held Friday, December 6 at NXP Semiconductors, Schatzbogen 7, 81829 Munich, Germany.
Accellera Forms UVM-AMS Working Group
Accellera recently announced the formation of the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG). The charter of the new working group is to develop a standard that will provide a unified approach, allowing UVM to be more mixed-signal aware which will improve the verification of analog/mixed-signal components and sub-systems. To find out more about the UVM-AMS WG read the press release or visit the UVM-AMS WG page. If you are not already an Accellera member and are interested in joining to participate in the working group and help shape the development of the standard, find out how to join Accellera.
Accellera Media Coverage
View recent media coverage of our standards efforts and working group activities. Coverage addresses topics such as IP Security, the global reach of our DVCon conferences and exhibitions, and the value of Accellera membership.
Accellera members have been very productive this past year developing new material on standards development and applications. From UVM and SystemC to IP Security and Portable Stimulus, we hope you find this information useful as you look through the tutorials, panel discussions, and new standards documents from 2019.
- IPSA Whitepaper: A whitepaper is available from the IP Security Assurance (IPSA) Working Group that describes Accellera’s initial proposal to address the industry’s security concerns involving IP integration. The whitepaper details the objectives of the IPSA standard and its approach, along with real-case examples highlighting the methodology.
- Public Repository: In July Accellera established a public repository for supplemental material related to its standards. The Accellera public repository is hosted at GitHub and will initially contain the SystemC reference implementation. It is available to the community to clone or fork for their specific use.
- SystemC Tutorial: Consisting of five parts, the tutorial “SystemC: Focusing on High-Level Synthesis and Functional Coverage for SystemC” was presented at DVCon U.S. 2019 by members of the SystemC Working Groups. It provides an overview on High Level Synthesis (HLS) with a discussion on data types and model structure as well as lessons learned. It also includes Functional Coverage for SystemC and a brief update on the Accellera SystemC Working Group.
- Cliff Cummings Tutorial on UVM: The tutorial, “Gain Valuable Insight into — and Make the Most Out of — the Changes and Features that Are Part of the New IEEE 1800.2 Standard for UVM,” was presented at DVCon U.S. 2019 is available for download. The tutorial addresses the changes and features that are part of the new IEEE 1800.2 standard for UVM.
- SystemC Panel Discussion: Laurie Balch from Pedestal Research moderated the Accellera-sponsored SystemC-focused panel at DVCon U.S. 2019 that explored what’s next and what should be next for the SystemC standard.
- Portable Test and Stimulus 1.0a: The Portable Stimulus Working Group incorporated errata for PSS 1.0 into the specification, making PSS 1.0a much easier for users to see the clarifications within the standard itself.
2019 Global Sponsors
Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.
Copyright 2019 Accellera Systems Initiative