Workshop: How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity

SystemCPresented at DVCon U.S. 2020 on March 2, 2020

HLS has long promised that it could deliver dramatic productivity by raising the level of abstraction, but there have always been questions regarding the fit of this technology and the results that it could achieve vs. hand-coded RTL and what an overall HLS design and verification methodology would look like.

This workshop begins with an introduction to the basic concepts of how HLS works to go from SystemC/C++ description to quality RTL. Then, the majority of the time consists of two leading semiconductor vendors discussing their real-world use cases and the results they have achieved. Matthew Bone of Intel describes their challenges and successful techniques for design space exploration and tuning of algorithmic and fabric-oriented designs. Rangharajan Venkatesan of NVIDIA describes their open source HLS library, MatchLib, and presents a case study for fast prototyping of a Machine Learning accelerator using object-oriented HLS methodology.

  • Part 1: A Brief Introduction to HLS -- Stuart Swan, Mentor, A Siemens Business
  • Part 2: Accellera SystemC Synthesizable Subset Standard -- Mike Meredith, Cadence Design Systems, Inc.
  • Part 3: Techniques for Optimization of Power and Performance using HLS -- Matthew Bone, Intel Corp.
  • Part 4: MatchLib-based Object-Oriented HLS Methodology -- Rangharajan Venkatesan, NVIDIA Corp.

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