Workshop: Hierarchical CDC and RDC Closure with Standard Abstract Models

Presented at DVCon U.S. 2024 by members of Accellera Systems Initiative

As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This tutorial covers the proven clock domain crossings (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential risk mitigation strategies. We will then discuss the hierarchical CDC/RDC verification methodology, the tradeoffs faced when incorporating units from multiple sources, and the challenges when integrating multiple vendor-generated abstracted blocks into an encompassing design. To mitigate these issues, we introduce the Accellera CDC committee, highlight the released CDC standard, and summarize the status of the current efforts.

The workshop is split into seven sections:

  • Part 1: Agenda
    Ping Yeung, NVIDIA
    (00:00)

  • Part 2: CDC-RDC Basic Knowledge
    Bill Gascoyne, Blue Pearl Software
    (3:00)

  • Part 3: CDC Setup & Constraints
    Kranthi Pamarthi of Renesas
    (10:46)

  • Part 4: Structural CDC/RDC
    Farhad Ahmed, Siemens EDA
    (17:46)

  • Part 5: Hierarchical CDC/RDC
    Farhad Ahmed, Siemens EDA
    (23:37)

  • Part 6: CDC Assertions
    Anupam Bakshi, Agnisys
    (26:34)

  • Part 7: Accellera CDC Working Group and Five Sub-groups
    Dammy Olopade of Intel; Anupam Bakshi, Agnisys; Kranthi Pamarthi, Renesas; Farhad Ahmed, Siemens EDA; Bill Gascoyne, Blue Pearl Software
    (30:39)

 

 

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