Workshop: Multi-Language Verification Framework Standardization and Demo

Presented at DVCon U.S. 2021

In this workshop, members of the Multi-Language Verification Working Group (MLVWG) present the current status of a proof-of-concept implementation and demonstrates its capabilities. A multi-language example is presented, which combines the UVM library in SystemVerilog and SystemC. Based on this example, the multi-language verification framework, its foundation concepts and the API targeted for standardization is explained and discussed. In addition, multi-language-specific UVM standardization requirements will be presented and language extensions will be proposed to address seamless integration and interoperability between UVM verification frameworks in SystemVerilog and SystemC.

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