VHDL Synthesis Interoperability Working Group

VHDL Synthesis Interoperability Working Group
IEEE PAR 1076.6
References

There is also an OVI/VI Synthesis Constraints Working Group, Here is a draft of their proposel (MIF format). To get on their vs-tsc e-mail list, click here and put the following in the body of the message: "subscribe vs-tsc [address]" where your e-mail address is optional.

A Rough draft of the recommendations for pragmas/metacomments/preprocessor directives Last Updated 9/9/96

The following files are references which were used to produce the Synthesis Interoperability Spec, they were provided for reference only by the companies noted.

VHDL synthesizable subset from Cadence

Autologic VHDL style guide from Mentor Graphics

Standard for Synthesizing from VHDL Language from Synopsys

Euopean VHDL Synthesis Working Group's Level-0 VHDL Syntesis Syntax and Semantics document.

Last Updated on 2/4/98
Please send feedback to David Bishop dbishop@vhdl.org