IP Security Assurance Proposed Working Group
The Accellera board recently approved the formation of a Proposed Working Group (PWG) to define an IP Security Assurance Specification. The PWG will remain active for a period of six months to explore the need for and requirements of a new standard to address this topic.
Chair: Brent Sherman, Intel
Currently there is no single standard that addresses security assurance in the development and delivery of intellectual property (IP) to Silicon integrators. With this proposed standard, user companies will be able to consume security assurance collateral in an automated fashion as part of the integration process.
With a single specification, user companies will be able to select the best tool(s) from competing vendors to achieve the best results for their products.
The initial scope for the Working Group is to define an automated systematic approach that can be consistently supported across multiple target implementations.
There is a certain level of risk when integrating third-party IP (3PIP) into Silicon. The risk stems from unknown behaviors that may occur once integrated, which could result as an exploitable vulnerability. Even if the source was provided, these unknowns may still exist since Integrators typically treat 3PIP as "black-box" technology. Silicon owners need a security assurance standard for acceptance before integrating 3PIP in order to minimize risk in their products. High-quality Silicon products are only such when they are built from high-quality IPs. The Proposed Working Group will collect requirements, identify technical feasibility, identify industry interest and acceptance, and provide a recommendation to start or not start a Working Group.
Join this Proposed Working Group
* For non-member participants some conditions apply. See the Accellera Policies & Procedures, Section 13 "Proposed Working Group Formation" for details.