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- 1076,3 Positions
- 1076.3 additions
- 1076.3 Summary Report to DASC (FDL2003)
- [Fwd: [vhdlsynth] Should we merge 1076.3 into 1076?]
- [Fwd: Final Call for Papers, NOTE 9/22/00 deadline extension]
- [Fwd: JOURNAL OF SYSTEMS ARCHITECTURE, Final Call For Papers]
- [vhdl-200x-ft] binary representation of "real"
- [vhdl-200x-ft] Bit directions
- [vhdl-200x-ft] Bit rules
- [vhdl-200x-ft] Bit Rules & methodology for handling math issu es
- [vhdl-200x-ft] Bit size rules
- [vhdl-200x-ft] More ideas on 1164 and 1076.3
- [vhdl-200x-ft] Read and write packages in numeric_std package
- [vhdl-200x] Should we merge 1076.3 into 1076?
- [vhdlsynth] "endian-ness" and bit-ordering
- [vhdlsynth] 1076.3 request for chair to issue a call for vote.
- [vhdlsynth] [Fwd: Annual EDPS 2007 Workshop announcement]
- [vhdlsynth] [Fwd: Last Call for Papers - EDP 2004 - Design Process Workshop]
- [vhdlsynth] binary representation of "real"
- [vhdlsynth] Bit Rules & methodology for handling math issues
- [vhdlsynth] Call for Contributions FDL 2003
- [vhdlsynth] Error in RESIZE function?
- [vhdlsynth] FDL'03
- [vhdlsynth] Fixed point arithmetic in 1076.3
- [vhdlsynth] fixed point packages
- [vhdlsynth] I test these p1lls it's amazing!
- [vhdlsynth] Meeting at DAC?
- [vhdlsynth] Merging with Fast Track
- [vhdlsynth] More ideas on 1164 and 1076.3
- [vhdlsynth] New VHDL packages on line
- [vhdlsynth] Original test routines for std_logic_1164
- [vhdlsynth] Read and write packages in numeric_std package
- [vhdlsynth] Refector changes - 1076.3 packages moved to vhdl-200x-ft
- [vhdlsynth] Should we merge 1076.3 into 1076?
- [vhdlsynth] Status of P1076.3
- [vhdlsynth] Status of P1076.3 + call for discussion of WG options
- [vhdlsynth] Status of P1076.3 + FINAL
- [vhdlsynth] Status of P1076.3 + FINAL!!!
- [vhdlsynth] Updated packages
- [vhdlsynth] vhdlsynth, 1076.3 - Where are we?
- [vhdlsynth] Visit Library Technologies at DAC 2007
- [vhdlsynth] Want to please your woman? u can do it!
- Base Types for Numeric_Std
- Ben's Proposal to add reduction operators to Numeric_Std
- BEN_P1
- Bit size rules (summary)
- Bug in and_reduce?
- Call for Papers IEEE/DATC EDP '99
- Call for Papers IEEE/DATC EDP 2000
- Call for Papers IEEE/DATC EDP 2000 - DEADLINE, 2/25/2000]
- Call for participation in VHDL std-logic WG
- CFP FDL'02
- Chair over the table
- Correction
- DATE'99 Call for papers
- dave_p3
- DDECS 2000 Call For Papers
- Different Concatanation result in VHDL -93 and VHDL -83
- Draft JIM_P1
- DSD2000 Symposium, First Call for Papers
- e-mail archive for vhdlsynth@vhdl.org
- EUROMICRO'99 Call for Participation
- EUROMICRO'99 DSD Workshop
- EUROMICRO'99 DSD Workshop, Call for Papers
- EUROMICRO'99: DSD Workshop - Last Call for Papers
- FDL conference
- FDL'98 Invitation
- FDL'99 Call for Contributions
- fixed point packages
- Flag Issue + Base Types for Numeric_Std
- Floating point synthesis
- Floating point synthesis, call for participation
- Force/release/get signals in hierarchy
- Hey guys!!
- How can generate Hardware from "IF then else" statement?
- How to get off the vhdlsynth reflector
- IEEE/DATC EDP 2000 - Advance Program
- IEEE/DATC Electronic Design Processes Mini-Workshop at ICCAD 1999
- Invitation to ballot: IEEE P1076.6 VHDL RTL synthesis standard
- Invitation to join VHDL Synthesis Working Group
- JASS Journal - Call for Papers
- JIM_P1: Any second?
- JIM_P1: Is it true?
- JIM_P1: J5, J6
- JIM_P2, Proposal: Logic Operators Array with Bit
- Joanne DeGroat
- laser printer supplies advertisement
- laser printer toner advertisement
- Logic Operators: Array with Bit
- NEW JOURNAL - CALL FOR PAPERS
- new release, numeric_std.vhd Oct. 3 testcompile
- Numeric_Std_TextIO Was Ben Cohen's thread on Numeric_Unsigned/Signed/Extra
- Numeric_Unsigned/Signed/Extra suggestions for next packages
- package update.
- Paul_P1
- Please take me off your email list.
- Precision of Arithmetic
- Problem with FT04
- Proposal DAVE_P1 - Add min, max, find_left and find_right
- Proposal DAVE_P1 - Add min, max, find_left and find_right operations
- Proposal JIM_P3: TO_X01, ...
- Proposal Rob_P1
- Proposal Rob_P1, => Rob_P2
- reduce pack for "numeric_bit"
- Reduction operators in Synopsys' std_logic_misc package
- Request for DC non-compliance examples.
- request for support of Unsigned + std_ulogic, Signed + std_ulogic
- Request to support Numeric_Std_Unsigned
- Revisions to Std 1164, std_logic_1164
- ROB P1: Additional functions.
- ROB P1: Proposal
- Semantics of assigning to 'X' and '-'
- Server down time
- Shift Operators
- Spammers
- Special Issue of JASS Journal
- Standards Due for Maintenance in 2003 - C/DA (2nd request)
- std_logic_1164 and synth packages revision
- std_logic_1164: CP-010 and numeric_std:Rob_P1
- Submission deadline extension for the Special Sessions on Modern Digital System Synthesis at SCI'2001]
- Support for NUMERIC_UNSIGNED
- Synopsys adds support for "numeric_std"
- synthesizable VHDL models
- test - please ignore
- Test Message
- the deadline for EUROMICRO'99 DSD Workshop is approaching
- This is a test of emerge
- too many functions?
- unsigned + Integer
- Unsigned + Integer and Fatal errors
- Updated numeric_std
- Updated numeric_std.vhd
- Updates to packages
- Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
- VHDL for synthesis.
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- Last message date: Fri May 18 2007 - 20:07:41 PDT
- Archived on: Fri May 18 2007 - 20:08:51 PDT