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IEEE VHDL 1076-1993 (The VHSIC Hardware Description Language) is designed for the description and simulation of digital systems. The standard, first approved in 1987 and later revised and reaffirmed in 1993, has gained wide acceptance in the last few years.
These documents specify extensions for VHDL-1076 to add support for the description and simulation of both conservative and non-conservative continuous and mixed continuous/discrete systems.
The work has been performed under the auspices of the Design Automation Standards Committee of the IEEE, VHDL Analysis and Standardization Group, under PAR 1076.1. The extended language is informally called VHDL-AMS.
Begin with an overview of the proposed extensions. Follow the links for detailed information about the new language features and the reasoning behind them. Look at the comprehensive index of examples to get a sense of how the extended language works in practice.
This work has benefited from proposals and criticisms offered by our colleagues involved in the VASG, whose assistance we gratefully acknowledge. The mistakes and omissions are our own. Your comments and criticisms will be very much appreciated, either directly to the authors or on the 1076.1 reflector.
to see the table of contents. Pick the name to see the
document itself.
VHDL 1076.1 Architecture
Quantities and
Terminals
Simultaneous Statements
Time in VHDL 1076.1
Mixed-Mode Simulation
Initialization and DC
Simulation in VHDL 1076.1
Solvability
Statistical Modeling
Simulation Control
Examples from Application
Domains
Mixed Netlists
Frequency Domain Modeling and
Simulation
Definitions for Ramp and Slew
Quantities
In addition, the following papers authored by other members of the Language Design Committee may prove useful: