Minutes of VHDL-A meeting in Hamburg

Chair: J. M. Berge (CNET, France Telecom)

Attendees:
Siep Onneweer (Philips)
Ulrich Becher (R. Bosch GmbH)
Antonio Acosta (University of Seville)
P. Sinander (ESA/ESTEC WDN)
Mark Basten (Lucas Advanced Engineering)
Berndt Arbegard (Ericsson)
Alain Vachoux (EPFL)
Ernst Christen (Analogy)
Ian Getreu (Analogy)
David Smith (Analogy)
Serge Garcia Sabiro (Anacad EES)
Jorg-Oliver Fischer-Binder (R. Bosch GmbH)
Dominique Rodriguez (Anacad EES)
Mart Altmae (Synthesia)
Helene Durantis (Thomson-CSF)
Hazem El Tahawy (Anacad EES)
Dan Fitzpatrick (Cadence)


o A first presentation of J.M. Berge pointed out the problem of the VHDL-A
status: Do we want VHDL1076.1 be a supplement or an extension to the 1076
standard? Do we propose to ISAC in our validation process?
The letter of J.M. Berge to J. Hines summarizes the decisions taken on these
topics (see annex).
o A short presentation of AVI has been done. The Analog VHDL International
initiative will support the IEEE 1076.1 effort. The two key domains in which
AVI will help the IEEE working group are the validation phase and the
documentation phase. A critique of the design work done up to now in the
framework of IEEE 1076.1 will be presented at the DASC meeting, the 15th of
October. Elements of this critique should be sent on the reflector before the
meeting.
o Presentations of the two (concurrent) versions of the LES on analog event
have been presented by Mart Altmae and J.M. Berge (transparencies of Denis
Rouquier). 
Since both versions appear to show a lack in their power of description (a
specific issue has been carried out by Ian Getreu), it has been decided to
first fix the problem and thus to re-present the two options at the next DASC
meeting.
o Ernst Kristen has presented the first elements on LES-R, related to
simulation control. A complete list of the interactions has been carried out.
No decision has been taken to enter (or not) these controls into the language
(or to predefine attributes for that purpose). Ernst should send these elements
to the reflector soon.
o Due to lack of time, the presentation of Serge Garcia Sabiro/ Dominique
Rodriguez on LES LL (Analog Subprograms) has been postponed to the DASC
meeting.

The following proposal for the DASC meeting agenda(15th of October) has been
carried out:

Morning:
o AVI presentation - Stan Krolikovski (COMPASS)
o Critique of the Language Design Work - Dan Fitzpatrick (CADENCE)
Afternoon:
o Analog Subprograms (LES LL) - Alain Vachoux
o Analog Event: solving the previous issue (J.M. Berge and Mart Altmae?)
o Elements on mixed-mode simulation cycle (Ernst Kristen)
o Validation outlines (Jorg-Oliver Fischer-Binder)

It has also been proposed to continue the meeting on Saturday 16th if room
available and enough people present.

Annex: (Sent to john Hines last week)

John,

During the VHDL-A working group meeting in Hamburg, a large majority of
attendees asked to present the following topic to the VASG (or the steering
committee if more appropriate) during the next DASC. Is it possible to put this
on the agenda.

The request concerns the status itself of the VHDL-A PAR. If our information is
correct, this PAR will lead to a VHDL supplement called VHDL.B. If this notion
of supplement is probably what is needed for the result of the shared variable
working group (VHDL.A), but seems inconsistent with our proposition.
I will be ready to elaborate on this at the DASC meeting but let us say that
our idea is to obtain an extension to the language (i.e. an LRM referring to
the VHDL LRM) and not a new version of VHDL. If we assume a positive ballot for
the shared variable result, the new version of VHDL (including the supplement)
will be the only official one. In the case of a positive ballot of VHDL-A, we
do not wish the result to be a single VHDL standard including analog
extensions. The result should not modify the VHDL standard but propose a
standard analog extension referring to it. 
The difference between the two approaches is considerable since many people
would probably vote negatively to a significant increase in the VHDL standard.

In the same spirit, we have started the validation phases of VHDL-A. Three
phases have been distinguished:
o User Validation: Do our extensions cover the needs? This validation is
"analog-designer-driven".
o Feasibility Validation: Is it possible to implement our extensions? This
validation is "vendor-driven" and mainly consists of the building of
prototypes.
o Language Validation: Are our extensions consistent with the consistency (and
philosophy) of VHDL? Our wish is that this last point will be "ISAC-driven" and
I would like to propose and discuss this idea during VASG. I also need 10
minutes for that.

Thanks,

Jean-Michel