IEEE 1076.1 working group meeting report
March 9 2005, Münich
==============================================================================

Report and related files are available at http://www.eda.org/vhdl-ams/.

Meeting attendees:
   Deepika Deverajan, Ansoft Corp.
   Uwe Feldmann, Infineon Technologies
   Joachim Haase, Fraunhofer IIS/EAS
   Yannick Hervé, CNRS-PHASE
   Roger Holden, Nokia
   Ralf Juchem, Ansoft Corp.
   Tom Kazmierski, Southampton University, WG Secretary
   Eckhard Lenski, Siemens AG
   Ekkehard Miersch, EFM
   Arpad Muranyi, Intel Corp.
   Olivier Rolland, Systems'VIP
   Sébastien Snaidero, Systems'VIP
   John Willis, FTL Systems
   Alain Vachoux, EPFL, WG Chair

Agenda:
   1. WG status update (Alain Vachoux)
   2. IBIS presentation (Arpad Muranyi, Intel Corp.)
   3. VHDL-AMS language direction (Alain Vachoux)
   4. Activities and meeting schedule (Alain Vachoux)
   5. Other business

Alain opened the meeting at 13h. Alain proposed that all attendees get their
email address registered in the 1076.1 mailing list, if not already done.
Proposition accepted unanimously.

1. WG status update
-------------------
See meeting slides #3 and #4.
Alain stressed the deliberately limited scope of the 1076.1 PAR. The new
1076-2005 and 1076.1-2005 LRMs are expected to be approved by December 2005.

2. IBIS presentation
--------------------
See meeting slides #5 and Arpad's slides (IBIS_presentation_2pg.pdf).
Arpad Muranyi gave an overview of the IBIS organization and the IBIS model
format, and presented a first list of points on which IBIS organization and
IEEE 1076.1 WG could collaborate.

Comments raised during Arpad's presentation (some on behalf of Ernst
Christen):
- [Slide 3] It is said that "IBIS files are not really models, they just
contain the data that will be used by the simulation tool's behavioral models
and algorithms." How are the data given semantics? Do IBIS keywords have
semantic meaning? Are the behavioral models or simulation algorithms specified
such that the data in IBIS files are portable?
Answer: Data in IBIS files include curves/tables or instances of ideal
primitive electrical components (e.g. resistors, capacitors, sources). IBIS
supports the Berkeley SPICE 3F5 format which is considered the lowest common
denominator between existing various SPICE format flavors.
IBIS keywords (between square brackets) are essentially tags that qualify the
kind of information (similar to XML).
- [Slide 7] Other reasons to support VHDL-AMS are to be able to cope with
arbitrary complex mixed-signal behavior, to provide better IP protection, and
to reduce simulation time.
- [Slide 9]
Table lookup functions: It has been agreed that developing a standard package
for table lookup functions would be needed and that other applications than
IBIS could benefit from it.
Resetable integration function: The VHDL-AMS language already provides a
mechanism to support resetable integration through the break statement.
Unfortunately, it is not yet fully supported in current EDA tools.
Common support of VHDL-AMS and Verilog-AMS: During the 1076.1 language design
phase, the WG proposed to define a unified semantic ground with Verilog-A
without success. Developing automatic language translators is a possible way,
although there may be issues when addressing mixed-signal capabilities which
are different in the two languages, particularly in the area of
initialization.
- [Slide 14] The "external circuit" section allows for providing references to
VHDL-AMS models. Parameters are mapped to generic parameters (parameter values
are missing in the slide). Port names are listed in two separate lists (one
for terminal ports and one for signal ports), but this is not mandatory.
Terminal ports are assumed to be of nature electrical. Signal ports are
assumed to be of type std_logic. The IBIS I/O Buffer Information Specification
version 4.1 of January 30, 2004 defines the format and the content of the
section.

It is expected that another IBIS presentation will happen at the next WG
meeting in US for getting other feedbacks and to define possible collaboration
further.

3. VHDL-AMS language direction
------------------------------
This was a first poll about the direction the language should take beyond the
coming LRM update. Time lacked for a real discussion, but the following points
have been raised:
- The 1076.1 steering committee should define a process for submitting and
reviewing new proposals. Each proposal should be supported by one or more
persons who are willing to drive the process. Mature proposals may be
developed further in separate subPARs (i.e. 1076.1.X) based upon 1076.1 WG
approval.
- Support of mixed netlists: Ernst Christen and John Shields are working on a
proposal. The latest publication on that topic is a paper at FDL'04.
- Support of nonlinear frequency (RF) domain: Uwe Feldmann agreed to provide a
requirement/white paper document.

4. Activities and meeting schedule
----------------------------------
Current WG activities are mostly oriented towards the coming LRM update and
the reaffirmation of the 1076.1 standard. The date of the next meeting has not
been defined yet, but it is likely a WG meeting will take place at the DAC
conference (June 13-17).

5. Other business
-----------------
None.

Alain closed the meeting at 14h30.