IEEE P1076.1 Working Group Meeting ================================== April 17, 2007 Nice, France Attendees --------- Alain Vachoux, Swiss federal Institute of Technology, chair Ernst Christen, Synopsys, Inc., vice-chair (by phone) Ken Bakalar, Mentor Graphics (by phone) Joachim Haase, Fraunhofer IIS/EAS Dresden (by phone) Manfred Maurer, Siemens Eckerhard Miersch, EFM Consulting John Shields, Mentor Graphics (by phone) Thuy Tran, Pyrotest (by phone) Agenda ------ 1. Agenda review 2. Approval of last meeting minutes 3. P1076.1-2007 revision status 4. WG organizational issues 5. Open discussion/AOB 6. Next meeting Alain opened the meeting at 19h30 MEST. 1. Agenda review ---------------- Alain reviewed the agenda and asked for new agenda items. John proposed to add a report on the new VHDL 1076 standard and on the SystemVerilog cross-language interoperability working group. We agreed the report to be done under point 5 of the agenda. 2. Approval of last meeting minutes ----------------------------------- The minutes of the last WG meeting held on September 19, 2006 in Darmstadt, Germany, was silently approved. 3. P1076.1-2007 revision status ------------------------------- See meeting slides #3 to #5. Alain gave an update on the P1076.1-2007 revision process. Ernst asked how long it will take to get the P1076.1-2007 LRM released by IEEE after RevCom approves the revision (June 6). Alain answered that Peter Ashenden, the P1076.1 LRM editor, will work with IEEE editors to produce the final LRM. All the P1076 and P1076.1 editing material is now included in a consistent FrameMaker package, so the generation of the final P1076.1-2007 LRM should be quick. How long it will take to IEEE to make the LRM document available is not yet known. Thuy asked how it will be possible to get the P1076.1-2007 LRM. Alain answered that the document will be available on the IEEE Standards Association and IEEE XPlore web sites and won't be free of charge. Alain will inform the WG of the URL when available. 4. WG organizational issues --------------------------- See meeting slides #6. Alain informed that the maintenance of the P1076.1.1 standard is now in the hands of the P1076.1 WG. Ernst mentioned that the packages are stable and no further work is planned. Alain proposed to check the expiration date of the P1076.1.1 PAR with DASC and IEEE. Alain mentioned that all WG officers have reached their 2-year terms and a new election round will have to take place. Thuy asked about the voting procedure and policies. Ernst answered that the WG Policies and Procedures document is available on the P1076.1 web site and that the document includes all the requested information. Ernst suggested that the election process should start only after the P1076.1-2007 revision is completed and proposed that Alain discusses with the DASC chair to prepare the process. Agreed. 5. Open discussion/AOB ---------------------- See meeting slide #7. Alain recalled the outcome of the last WG meeting about what is proposed to be done after the 2007 revision has completed. Three main topics have been identified and related champions defined. Ernst asked Ken whether he would be willing to contribute to the Mixed Netlist white paper as there are open elaboration issues that require detailed VHDL language design knowledge. Ken accepted. Ernst proposed to provide a white paper based on the chapter of the FDL'04 book with some updates. Joachim informed that a first draft document on table data types and lookup functions is available. Alain informed that Yannick Hervé confirmed his intent to develop his proposal for supporting requirement and specification further. Ernst suggested to have a new page on the P1076.1 web site to gather the documents related to proposals for new features. Alain replied that he will organize such a page, inform the WG and ask for feedbacks. John then made a report on two ongoing activities that may be of concern to the 1076.1 WG: the revision of P1076 and the SystemVerilog interoperability with other HDLs (e.g. VHDL(-AMS), Verilog-AMS, SystemC). IEEE RevCom approved the P1076c (VHPI - VHDL Procedural Interface) on March 2007 as a new amendment to IEEE Std 1076-2002. John asked about the status of a VHPI-AMS. Ernst replied that some work on that has been done but now the effort is dormant and no reactivation is planned. VHDL 200X is in the works under the Accellera umbrella. An approved Accellera standard is going to be forwarded to IEEE for ballot. New VHDL features include, among others: - Direct support of PSL - IP protection mechanism - Foundation to object-oriented modeling (e.g., formal generic types for subprograms and packages) - Fixed-point and floating-point packages - New composite types with unconstrained arrays - Hierarchical references. See http://www.accellera.org/apps/org/workgroup/vhdl/download.php/934/date_vhdl_tutorial.pdf for a more complete presentation. The next step is to define more OO and verification features in the VHDL language. The SystemVerilog Interoperability Technical Committee is a subcommittee of the IEEE P1800 SystemVerilog Technical Comittee that started in Fall 2006 (http://www.eda-stds.org/sv-xc). Its goal is to define how SystemVerilog can operate with other HDLs. This addresses topics such as type compatibility, library management, simulation cycle, component instantiation, module definition. Currently, the considered HDLs are SystemC, VHDL and Verilog-AMS/SPICE. The TC is gathering requirements through a survey. John agreed to post the survey announcement to the 1076.1 mailing list to get inputs on VHDL-AMS. 6. Next meeting --------------- Ernst agreed to investigate possibilities to have a WG meeting at DAC (San Diego, USA, 4-8 June). Alain mentioned that he is ready to organize a WG meeting at FDL (Barcelona, Spain, 18-20 September). Alain closed the meeting at 21h15 MEST.