VHDL Issue Number: IR1.99.02 Classification: Typographical error Language Version: VHDL-1076.1'99 Summary: Related Issues: Relevant LRM Sections: 5.4 Key Words and Phrases: step limit specification Current Status: Analyzed 1076.1-99 Disposition: Unknown Closed (All Issues Completely Addressed) Bugs Fixed, Enhancements Outstanding (No ISAC Issues) Superseded (ISAC Issues Outstanding) Disposition Rationale: Superseded By: N/A ----------------------- Date Submitted: April 12, 2000 Author of Submission: Kenneth Bakalar Author's Affiliation: Mentor Graphics Author's Post Address: Author's Phone Number: Author's Fax Number: Author's Net Address: Kenneth_Bakalar@mentorg.com ----------------------- Date Analyzed: 1 Jul 2005 Author of Analysis: Ernst Christen Revision Number: 3 Date Last Revised: 6 Jul 2005 EC: new numbering 10 Jul 2005 EC: changed status Description of Problem ---------------------- The definition of the step limit specification in section 5.1 of the LRM, last paragraph before the example, uses the phrase "it is an error" inappropriately. That language is used to describe a mistake of the modeler that must be detected by the language processor, not a requirement on the language processor when interpreting a legal model. Proposed Resolution ------------------- 1076.1-ISAC Analysis & Rationale -------------------------------- The sentence in question reads: If the value of a quantity is determined at time T, it is an error if the value of that quantity is next determined at a time greater than the value of T plus the value of the step limit expression evaluated at time T (see 12.6.6 for the process by which the analog solver determines the values of quantities, and 12.6.4 for the role that the analog solver plays in the simulation cycle). As pointed out by the author, the phrase "it is an error" is intended to refer to errors that the language processor must report. However, this sentence defines a property of the run time behavior that a model writer ca rely on. The issue can be addressed by rewording the sentence as follows: If the value of a quantity is determined at time T, its value is next determined at a time that is not greater than T plus the value of the step limit expression evaluated at time T (see 12.6.6 for the process by which the analog solver determines the values of quantities, and 12.6.4 for the role that the analog solver plays in the simulation cycle). 1076.1-ISAC Recommendation for IEEE Std 1076.1-1999 --------------------------------------------------- No change necessary 1076.1-ISAC Recommendation for Future Revisions ----------------------------------------------- Replace the offending sentence by If the value of a quantity is determined at time T, its value is next determined at a time that is not greater than T plus the value of the step limit expression evaluated at time T (see 12.6.6 for the process by which the analog solver determines the values of quantities, and 12.6.4 for the role that the analog solver plays in the simulation cycle).