IEEE PAR 1076.1 VHDL Analog Extensions


VHDL-A Design Objective Rationale

Version: 1.3
Date: 6 sep 95


Document history:

1.3      6 sep 95   Alain Vachoux
                    Integration of comments from vote on DOD 2.2.

1.2     23 jun 95   Alain Vachoux
                    Modified to reflect changes in DOD 2.2.

1.1      8 nov 94   Alain Vachoux, with Dan Fitzpatrick and Richard Shi
                    Augmented version related to DOD 2.1.

1.0        mar 94   Richard Shi
                    Initial version.


1. Introduction
---------------

VHDL-A is an extension of VHDL, currently under development by the IEEE DASC 
1076.1 Working Group, for the description and simulation of mixed analog and 
digital circuits and systems. The VHDL hardware description language was 
primarily designed for the modelling and the simulation of digital devices. 
During initial phases of the 1992 restandardization of VHDL, it was recognized, 
among other changes, that augmenting the language to handle analog designs was 
worthwhile. Due to the overwhelming number of requirements already in 
consideration for enhanced digital functionality, the 1076 standardization 
committee elected to create a separate VHDL-A working group, officially 
numbered 1076.1, to deal with the problem of adding analog capabilities to 
VHDL. The intention was to decouple the analog requirements from the '92 
language and to encapsulate them in a new standard that would be possibly 
merged with VHDL 1076 when the next restandardization occurs in 1997. As the 
time of this writing, it is more likely that VHDL-A will stay as a separate 
standard, VHDL 1076 addressing only the digital hardware. It was also decided 
that the evolution of VHDL-A would follow the same process as for VHDL'92, 
e.g., requirements gathering, requirements analysis, language design, and 
finally balloting.

The results of the first two phases, i.e. requirements gathering and 
requirements analysis, are contained in two separate, but related, documents: 
the Design Objective Document (DOD) and the Design Objective Rationale (DOR), 
this document.

The DOD lists a number of design objectives (DO) the VHDL-A language will have 
to meet according to some priority. Each DO is briefly justified in a short 
rationale. Also, the list of design requirements (DR) as collected in the first 
phase, is given and a cross-reference between DOs and DRs is available.

The DOR aims at more complete justification of the VHDL-A design objectives. 
Specifically, it provides interpretations or explanations to the design 
objectives whenever necessary. It describes why such design objectives are 
required, if possible what are consequences or implications to language design, 
and why and how various trade-offs have been made while there is a conflict. In 
addition, this document records guidelines and various considerations used by 
the IEEE 1076.1 Design Requirement Subcommittee in preparing the DOD.

This document is structured as follows. Section 2 describes and justify the 
guidelines for the preparation of the DOD. Section 3 covers the rationale for 
the scope of VHDL-A. Sections 4 and 5 describes the rationales for the 
structure aspect and behavior aspect of the design objectives of VHDL-A. 
Rationale for the simulation related aspect is presented in Section 6. Section 
7 presents design objectives related to interface between analog and digital 
descriptions. Concluding remarks are made in Section 8.


2. Guidelines of the Design Objective Document
----------------------------------------------

There are seven basic guidelines used by the IEEE 1076.1 Design Requirement 
Subcommittee in the preparation of the DOD. They are described as below.

    1. The DOD must contain a list of as much consistent as possible design
       objectives.

    2. The DOD must assign a priority to each design objective. Three orders
       are identified as *must*, *should*, and *desirable*.

       *must*
            The objective is a basic fundamental requirement and cannot be
            compromised.

        *should*
            The objective provides useful functionality beyond the basics and
            provides significant benefits if met. Unmet *should* objectives can
            be used as a basis for requirements in subsequent
            re-standardizations.

        *desirable*
            The objective will enhance the usability and/or performance of the
            design. However, if not met, overall performance will not be
            severely compromised. 
            Additionally, desirable objectives are to be used as a basis for
            new requirements in subsequent re-standardizations.

    3. The DOD must not impose unnecessary constraints on language design. 
       Design objectives related to the end user requirements must be stated as
       objective as possible, i.e., independent of language design styles  or
       approaches. Design objectives concerning the compatibility with VHDL
       must be specified carefully in order to give the VHDL-A language
       designers as much freedom as possible in pursuing high quality language
       design.
     
    4. The DOD must be self-contained.

    5. The DOD must be justified. However due to the space limitation and also
       for the clarity of the DOD, only a short rationale or remark is given
       for each DO.

    6. Each DO can stand in its own and has a unique interpretation.
    
    7. Each DO must be stated as compactly as possible. No attempt is made in
       the DOD to give a detailed explanation of each DO.


3. Scope of VHDL-A
------------------

The scope of VHDL-A defines which kind of systems it describes and which type 
of simulation it targets. In this section, we present design objectives related 
to the scope of VHDL-A. Also the relation with VHDL and the general guidelines 
in handling analog and digital descriptions are defined here.


DO1  (must)
     VHDL-A must be suitable for the description and simulation of digital,
     analog, and mixed digital/analog systems at several abstraction levels
     (i.e. functional, behavioral, macromodel, and device levels).
     VHDL-A must be able to support any design methodology and be technology
     independent.

DO2  (should)
     VHDL-A should be suitable for the description and simulation of
     non-electrical (i.e. mechanical, thermal, etc.) and mixed
     electrical/non-electrical systems.

DO3  (must)
     VHDL-A must be a "super-set" of VHDL'93. Any description that is valid in
     VHDL'93 must also be valid in VHDL-A, with the same simulation results.
     The only permitted exception to this is that new keywords introduced into
     the language may conflict with identifiers used in a VHDL'93 description.

DO4  (must)
     VHDL-A must at least support time-domain analysis of lumped-element 
     electronic systems.

DO5  (must)
     Analog descriptions must re-use existing (VHDL'93) syntax where
     appropriate.

DO6 (should)
     VHDL-A should support time-domain analysis of lumped-element 
     non-electrical systems.

DO7  (must)
     VHDL-A must support small-signal linear frequency analysis of
     lumped-element electronic systems.

DO7b (desirable)
     It is desirable that VHDL-A support large-signal non-linear frequency
     analysis of lumped-element electronic systems.

DO8  (should)
     VHDL-A should support small-signal linear frequency analysis of
     lumped-element non-electrical systems.

DO8b (desirable)
     It is desirable that VHDL-A support small-signal linear and large-signal
     non-linear frequency analysis of lumped-element non-electrical systems.

DO9  (must)
     VHDL-A must support the noise modeling and analysis of lumped-element
     electronic systems.

DO9b (should)
     VHDL-A should not be restrictive in other types of analyses.

DO10 (must)
     VHDL-A must provide mechanism(s) that allow the analog and digital
     behavioral parts of a mixed description to interact.

DO11 (must)
     The basic A/D and D/A interaction mechanisms of VHDL-A must be completely
     defined and make no use of the "foreign interface" of VHDL'93.

D012 (should)
     The model of the interface between the analog and digital descriptions
     should be customizable by the user.


---- Analog hardware description language (DO1)

VHDL-A is intended to be an analog hardware description language (AHDL). As 
such, it must allow the direct specification of both the behavior and the 
structure of hardware systems. A primary motivation for analog hardware 
description languages is to support the modelling of physical systems. An AHDL 
must therefore allow one to model the physical conservation laws, such as the 
energy conservation law which states that energy can neither be created nor 
destroyed, but it can only changes its form. The distinction between analog and 
digital systems occurs whenever the designer selects how the system or parts of 
it will work. Both encompass different design methodologies and trade-offs. 
Roughly speaking, digital behavior is event-driven and therefore takes care of 
a limited number of well defined states, while analog behavior is continuous 
and takes care of whole waveforms.

To be consistent with the VHDL philosophy, VHDL-A must at least support the 
simulation of the specification. The standard VHDL simulation cycle uniquely 
defines the semantics of the language and is therefore an essential feature to 
ensure portability. The aspects related to analog and mixed digital-analog 
simulation will be discussed later in this document.

It is very desirable that VHDL-A supports analog synthesis also. However, 
because analog synthesis is still in its infant stage, we do not know exactly 
whether the semantics for supporting synthesis is significantly different from 
simulation. Therefore, it is not the objective of the current version of VHDL-A 
to support synthesis. However, whenever possible, VHDL-A must not make 
assumptions that may restrict its ability in supporting synthesis, or may 
restrict its future extensions for supporting synthesis. As a remark, 
particular emphasis must be given to support mixed-level abstractions, since it 
will be very helpful in supporting synthesis.

An AHDL standard is extremely useful for ASIC design industry. One of the major 
problems that designers face today is the consistency of their designs. No 
simulators on the market today can give them all the answers they need, so they 
have to  use different tools, each requires different syntax for describing  
the same circuit. A standardized language is necessary to provide the design 
development, simulation, and data exchange of a hardware system.


---- Design methodology independence (DO1)

A key to managing the complexity of a large design is to use top-down and 
bottom-up hierarchical design methodologies. Such designs usually contain 
mixed-level description. Further, the development of a large system may involve 
more than one team, each team may base their design on different methodologies. 
Finally, design of  large systems nowadays may involve the use of existing 
design units. All these call for the need to support any design methodology, 
for which the ability to handle mixed levels of abstraction is essential.

A top-down approach starts from abstract descriptions that intend to capture 
essential aspects of the design while deliberately ignoring implementation 
details. These abstract descriptions are progressively refined until they reach 
a point where one implementation that satisfies the design requirements may be 
directly inferred from the description. A bottom-up approach takes the opposite 
way, by starting from a set of descriptions of pre-defined components, and by 
assembling them to form more complex components. In the EDA world, top-down 
design is usually associated with synthesis, while bottom-up design is usually 
associated with verification.


---- Support of many abstraction levels (DO1)

Depending on the complexity, the design will encompass several hierarchical 
descriptions at several levels of abstraction. Abstraction levels are today 
well defined for digital design. A level of abstraction defines three aspects: 
the modelling concept, the timing model and the observable values. For 
instance, at the register transfer level, the modelling concept is guarded 
commands (reactive behavior), the timing model is discrete real time (clock 
ticks) and the observable values are interpreted bitstrings. It is usual to 
consider the abstraction levels from system (most abstract) to gate (less 
abstract) as pertaining to the digital world. For the most detailed level, the 
electrical, or circuit, level, the modelling concept is differential equations, 
the timing model is continuous real time and the observable values are 
continuous reals. This level is usually considered as to pertain to the analog 
world. It does not however cover all possible modelling methodologies as far as 
analog design is concerned.

Abstraction levels for analog design are less well established. In addition to 
the circuit level, other levels may be defined for more abstract analog 
descriptions. The main difference with digital levels is that analog 
abstraction levels are based on continuous time, while digital ones are based 
on discrete time. Possible analog abstraction levels are, from the most 
abstract to the less abstract:

- Functional level: The modelling concept is based on signal-flow descriptions 
where a mathematical expression (e.g. a transfer function) maps the system 
input to the system output in a unidirectional way. Observable values are 
continuous values that do not depend on conservation laws such as Kirchhoff¹s 
laws for electrical systems.

- Behavioral level: The modelling concept is based on equations that describe 
the constitutive relations of components. From this level down to circuit 
level, observable values are continuous values that depend on conservation laws 
such as Kirchhoff¹s laws for electrical systems (e.g. voltage and current).

- Macromodel level: The modelling concept is based on the hierarchical assembly 
of lower level, circuit, components such as controlled sources. Only the very 
minimum number of these components are used to approximate the intended I/O 
behavior. The structure of a macromodel is usually simpler than the underlying 
hardware. The macromodel level is not always considered as an abstraction level 
as such, but rather as a specific style of description.

- Circuit level: The modelling concept is based on the hierarchical assembly of 
primitive components such as resistors, capacitors, transistors, sources, whose 
behaviors are pre-defined. The structure of a circuit description usually 
matches that of the underlying hardware.

- Device level: The modelling concept is based on two- or three-dimensional 
equations describing the behavior of one specific device (e.g. a transistor). 
Observable values are the electrical characteristics of the device, such as I/V 
characteristics.

- Process level: The modelling concept is based on quantic physics where 
aspects such as geometries and doping profiles are taken into account.

VHDL-A must support all levels of abstraction from the functional level to the 
circuit level. The device and process levels are out of the scope of VHDL-A 
because descriptions at these levels are too much detailed to be handled 
efficiently in the context of the design of a whole system. Useful information 
from these levels is usually translated into equivalent, more abstract, data 
expressed at the circuit level to perform analog or digital design. For 
example, detailed data from the device level are used to derive and validate 
circuit-level transistor models that can be handled by electrical simulators 
such as SPICE. Another example at the process level is the influence of the 
manufacturing process which is translated into statistical distributions on 
circuit component values.


---- Technology independence (DO1)

There are three basic reasons for hardware description languages to support the 
description and simulation of mixed IC analog and digital systems.

First, a large portion of systems being designed nowadays, in particular ASICs, 
have a part of digital functionality, and other part of analog functionality. 
These are usually called mixed digital/analog circuits/systems.

Next, high performance and high speed digital circuits exhibit analog 
behaviors. Their timing characteristic and power consumptions for example 
cannot be only considered at the digital level (called digital abstraction). A 
full chip/system simulation of such a system requires that some part of the 
system be described at analog abstraction level, and some part be described at 
the digital abstraction level.

Finally, description of analog systems, particularly at the behavior level, may 
require techniques usually associated with the digital abstraction level. This 
is especially the case for certain non-IC applications.


---- Support of non-IC systems (DO2)

Hardware systems that exhibit analog behavior are not confined to electrical 
circuits. Also, in many modern systems it is not sufficient to model and to 
validate only the behavior of the electrical part. In power applications, for 
instance, the thermal properties must be considered to get an accurate picture 
of how a system works. Other examples are electro-mechanical (mechatronic) 
systems, sensors etc. It is also natural to extend the scope of VHDL-A to  
support non-electrical systems as they are analogous to the electrical systems 
in their modeling requirements. The differential equations which describe state 
variable solutions of systems in the mechanical, thermal, etc. disciplines, are 
of the same form as the differential equations in the electrical discipline.

VHDL-A should therefore support any system that can be described as a set of 
nonlinear ordinary differential and algebraic equations. This also includes 
thermal, mechanical, rotational, etc. systems in any combination. Since there 
are commercial HDLs on the market that support this ability, customers expect 
that VHDL-A does the same. Actually, the success of commercial HDLs provides 
the evidence that the ability of supporting mixed discipline systems is not 
only important, but also feasible.

There are two possible implications to language design. First, certain 
facilities may need to provide to the user convenience, for example, the 
ability to specify explicitly which discipline a component is. Next, care must 
be taken in language design as not to use unnecessary assumptions that might 
limit the power of the language, for example, the use of specific electrical 
terminologies. Indeed this is very much consistent with the VHDL design 
philosophy. A main feature of VHDL is to provide programming abilities, rather 
than concrete language constructs, for describing concrete components. For 
example, although VHDL is a digital hardware description language, however, no 
built-in constructs for logic gates are provided. This is part of the reason 
why VHDL has attracted attentions from a wide range of application domains.


---- Support and re-use of VHDL¹93 (DO3, DO5)

VHDL is an IEEE standardized digital hardware description language. It has been 
widely accepted for the description and simulation of digital systems. Its 
applications are growing into various areas beyond its original design 
objectives, for examples, synthesis and testing. The development of VHDL itself 
also needs to consider analog modeling capacity in order to meet customer 
needs, especially for those customers in mixed system design.

VHDL has a rich ability in supporting large designs and design reuse, with 
techniques borrowed from software engineering. This ability is highly desirable 
to analog and mixed system designers. Thus, VHDL-A, built on top of VHDL, will 
gain additional advantages. Also, simulation is the most widely used and mature 
part of CAD. Simulation of systems with mixed abstractions, regardless whether 
they are mixed functionality systems, or mixed abstractions for the same 
functionality systems, calls for a unified language. Such a unified language is 
expected to give designers a friendly interface around which various simulation 
tools can be well integrated. A unified language is expected to be helpful in 
developing future simulation tools that may span over a computer network in 
order to handle the continuously increasing need in simulation capacity.

VHDL-A is decided to be designed as an extended VHDL (VHDL-A = VHDL¹93 + analog 
aspects). This is due to two considerations. First, it is for the purpose to 
re-use those existing models and libraries developed in VHDL. Next, it is to 
ease the acceptance of VHDL-A by the digital design community. In the other 
words, we are not allowed to change existing VHDL unless we come up with a 
solution for reusing these existing design libraries and design tools, and a 
convincing and easy acceptable reason to existing VHDL users to re-learn their 
language. There are two basic interpretations of the superset concept here, 
which may affect fundamentally how VHDL-A language design proceeds. A 
straightforward interpretation is that VHDL-A keeps everything in VHDL (except 
for some keywords) ---syntactic constructs and their semantic rules--- with 
addition of specific constructs for handling analog description and simulation. 
We can also interpret the superset concept in a border sense: all constructs 
and semantics in VHDL-A degenerate to existing VHDL¹s if only digital 
description and simulation are concerned. In terms of the set concept, this 
means that not only the elements in the set can be enlarged, but also each 
element in the set can be enlarged.


---- Support of analog simulation techniques
     (DO4, DO6, DO7, DO7b, DO8, DO8b, DO9, DO9b)

Analog, or circuit, simulation is one of the oldest CAD activity in electronic 
design. One of its main characteristics is that it ecompasses many different 
kinds of analyses, as well as many different techniques to implement them in a 
simulator. Time-domain circuit simulation is reportedly one of the most used, 
although the most costly, means to verify the behavior of an analog system 
without breadboarding. Moreover, mixed digital-analog modelling and simulation 
requires naturally to have time-domain description and simulation capabilities 
from both digital and analog sides.

Assuming lumped-element descriptions of the system to simulate is also a 
consequence of the support of abstraction levels from circuit to behavioral 
level. As such, the microwave domain is not taken into account.

Given the wide use of the SPICE circuit simulator, it is natural for VHDL-A to 
support at least all the kinds of analysis SPICE supports, namely: DC, 
transient, small-signal AC, noise and distortion analyses. A time-domain 
description in VHDL-A, either behavioral or structural, should allow all these 
analyses, as SPICE already does from a netlist description.

Other types of analysis, especially power consumption, frequency-domain 
analysis, sensitivities, statistical, harmonic balance, are desirable to be 
supported by VHDL-A. Care must be taken to ensure that these analyses can be 
supported as much as possible, because analog designers are not only interested 
in time-domain response of the system, other type of performances are of 
equally, or very important also for designing an analog system. However, the 
precondition here is that such considerations do not complicate too much with 
existing VHDL syntax and semantics. So whenever possible, VHDL-A should use as 
few assumptions as possible that might restrict other types of analog analyses.


---- Mixed digital-analog interactions (DO10, DO11, DO12)

Direct interaction of analog and digital components is not possible because 
they are not handled by the same simulation kernel. By simulation kernel it is 
meant a standard mechanism that defines precisely how the VHDL-A statements 
have to be handled during simulation. Obviously, digital statements will not be 
handled the same way as analog staments, even if they are encapsulated in the 
same description. Therefore, VHDL-A assumes that two different simulation 
kernels exist.

Given this, a mechanism must be established to translate signals from 
analog-to-digital and vice versa. Translation involves in general both a value 
conversion and a conversion between two timing models. These aspects will be 
discussed later in this document.

Care must be taken to ensure portability. VHDL-A will define a mixed simulation 
cycle based on A/D and D/A interactions. These ones are not allowed to vary 
between implementations since they will be part of the norm. VHDL¹93 provides a 
way to affect portability through the use of the ³foreign interface² 
capability. VHDL-A must not make any use of such a feature, since it allows to 
defer the implementation of some part of the description outside VHDL-A. This 
is an open door to different implementations and therefore contradicts the 
portability objective.

Another point is to allow the user to decide where to use A/D and D/A 
conversion mechanisms and also how they will work (i.e. how the translation 
between signals will be performed) during simulation. This is necessary for 
VHDL-A to be technology independent.


4. Structure aspects
--------------------

In this section, we describe and justify the design objectives that relate to 
the structure description in VHDL-A.


DO13 (must)
     VHDL-A must be capable of describing a digital, analog, and mixed
     digital/analog systems by structural composition of components.

DO14 (must)
     Structural descriptions consisting of analog components of analog 
     behaviors must observe conservation-law and/or signal-flow semantics.

DO15 (should)
     VHDL-A should provide a migration path for SPICE based libraries and
     system descriptions (i.e. netlists).

DO16 (desirable)
     It is desirable that VHDL-A provides a mechanism to specify netlists
     conditional upon the value of a constant parameter (conditional netlists).
     A special case of this is collapsing 2 nodes.

DO17 (desirable)
     It is desirable that VHDL-A provides a mechanism to specify regular array
     structures of instances, with constant dimensions.


---- Structure description (DO13, DO14)

A system is usually built from a connected network of components. Depending on 
the complexity of the system, components may be further decomposed 
hierarchically into another set of interconnected, lower-level, components. 
Finally, leaf cell components have to encapsulate some behavior if the 
description is intended to be simulated. Connection points in the network of an 
analog system are called nodes. Terminals of components are called pins. There 
are two types of networks: conservation-law and signal-flow, dependent of the 
semantics of connection.

An example of conservation-law networks is electronic circuits. In a 
conservation-law network, there is a so-called through quantity (current for 
electronic circuits) associated with each branch, and a so-called across 
quantity (voltage for electronic circuits) associated with each node. Usually, 
but not necessarily, the product of the through quantity by the across quantity 
is a power. This will depend on the modelling requirements. For example, a 
model of a mechanical system may be written using through quantities to be the 
force and across quantity to be the position. The product across by through is 
a work in that case.

Conservation-law networks have also a specific connection semantics, namely 
Kirchhoff¹s laws for electronic circuits. For each node in such a network, the 
algebraic sum of through quantities associated with all the branches entering 
that node must be zero (KCL for electronic circuits). For each loop, the sum of 
the across quantity drops along the loop is zero (KVL for electronic circuits). 
Conservation-law networks are also directionless: connecting two components 
together implies a mutually-shared contribution to each other¹s behavior.
Conservation-law networks are supported from the circuit abstraction level up 
to the behavioral abstraction level. They are moreover required to support the 
description of lumped-element systems (either electronic or from other 
disciplines).

Examples of signal-flow networks can be found in the early stage of an 
electronic system design or in a control system design. In a signal-flow 
network, quantities are associated with nodes only. The signal-flow semantics 
imposes that the terminals through which different components connect together 
have the same quantity. It also imposes a directed interaction between nodes. 
Signal-flow networks are useful to describe linear systems. A more general form 
is block diagram description which may represent any kind of nonlinear 
operation to be performed on quantities entering a block. Signal-flow networks 
are supported at the functional abstraction level.

In addition to the high level description of analog systems, the signal-flow 
semantics is required to model the phenomena that one component is controlled 
by a quantity associated with terminals of another component. Take a 
voltage-controlled current source I = f(V) for an example. Suppose that V is 
the voltage of a terminal of COMPONENT_A and the voltage-controlled current 
source is used inside COMPONENT_B. Then we have to import V into COMPONENT_A 
through its interface (more precisely in VHDL, its entity declaration). We 
could have something like COMPONENT_B(V, pin1, pin2,...), where pin1 and pin2 
are two electrical terminals of COMPONENT_B. Here, binding for V obeys the 
signal-flow semantics, where bindings for pin1 and pin2 obey the 
conservation-law semantics.

The signal-flow semantics is the simplest binding rule for analog system 
specification. However, it is not supported as a generally available structure 
mechanism in SPICE-like simulators, which are originally developed with the 
emphasis on integrated circuits consisting of a limited number of primitive 
components. Incorporation of the signal-flow semantics into VHDL-A will not 
complicate the language, but give rise to more power, and lead to more 
applications, such as control system simulation and possibly analog synthesis.


---- SPICE compatibility (DO15)

SPICE is undoubtedly the most widely used analog simulator. Its associated 
syntax has hence become a de facto standard, although many flavors of it exist 
on the market. The acceptance of VHDL-A will then depend on how the language 
will allow the SPICE users to re-use existing SPICE netlists. However, the 
objective is neither to include the SPICE netlist format (actually which one?) 
in VHDL-A, nor to allow VHDL-A to understand it. VHDL-A should be powerful 
enough to allow the translation of a SPICE netlist into a VHDL-A description, 
possibly through the use of automatic tools (it is always easier to translate a 
simple format into a more complex one than the other way around).

Nothing prevents some future VHDL-A tool to support SPICE netlists, however. 
Some VHDL tools already provide this feature to allow mixed mode modelling and 
simulation without any modification on the language itself. The use of VHDL¹93 
foreign interface mechanism, or the development of specific dedicated packages 
should also help.

Another aspect of SPICE compatibility is the fact that many device models are 
available in SPICE-like simulators. These models are usually hardcoded into the 
simulator (1) because there is not any standard procedural interface to allow 
to plug one device model into any simulator, and (2) for efficiency reasons (on 
the average about 80% of the total simulation time is spent in model 
evaluation). Programming constructs of VHDL-A should allow these models to be 
rewritten in VHDL-A. However, efficiency reasons may force to keep them 
hardcoded into the simulator. A VHDL-A description of a device model might be 
useful for prototyping purposes anyway.


---- Conditional netlists (DO16)

The need to switch netlist description for a component *before* simulation 
arises frequently in the analog design process. Drain and source parasitic 
resistances in a MOS model are a typical example: a non zero value forces the 
netlist to have one or two supplementary nodes. Node collapsing is the opposite 
situation (due to a short-circuit for example). Higher level models should also 
gain flexibility from conditional netlisting.

Switching between a behavior model and a netlist model should also be 
supported, since behavior and structure could be freely mixed in the same 
description, something VHDL already allows.


---- Regular structures (DO17)

The ability to specify regular analog array structure is useful for designing 
such circuits as artificial neural networks. VHDL already provides the 
"generate" statement that could be used as a base to meet this objective.


5. Behavior aspects
-------------------

So far, VHDL-A will basically provide what SPICE already provides, although in 
the more powerful context of VHDL. The development models of complex systems 
may however no more rely on structural modelling only, because the use of 
pre-defined low level components in a bottom-up approach inherently limits the 
descriptive capabilities of the language. In this section, we describe and 
justify for the design objectives that relate to the behavior description in 
VHDL-A.


DO18 (must)
     VHDL-A must support behavior specification of an analog system by a
     set of linear/nonlinear differential/algebraic equations and/or by a
     sequence of assignments.

DO19 (must)
     VHDL-A must support the description of continuous time behavior both by
     explicit and by implicit equations.

DO20 (must)
     VHDL-A  must support mixed structural and behavior specification for a
     single analog component. For this purpose, VHDL-A must provide a mechanism
     for the behavior specification portion to access quantities associated
     with the structural specification portion and vice versa.

DO21 (must)
     VHDL-A must provide a mechanism to access quantities that are used inside
     an analog component but not associated with terminals (i.e. connection
     points satsfying the KCL/KVL semantics) from outside of the component.

DO22 (must)
     VHDL-A must support a mechanism to parameterize a model. The support
     must at least include parameters that are constants (static parameters).
     It is desirable to support parameters that vary during simulation (dynamic
     parameters).
     It must be possible to distinguish parameters that intentionally have been
     left unspecified from parameters having their default initial value.

DO23 (must)
     VHDL-A must support the description of analog behavior that depends on the
     independent variable of an analysis.

DO24 (must)
     VHDL-A must support discontinuous analog behavior and waveforms. In
     particular, it must be possible to enforce an analog time step in response
     to some change in the analog part.

DO26 (must)
     VHDL-A must provide a time derivative operator.

DO27 (must)
     VHDL-A must provide pre-defined mathematical functions (such as sine,
     cosine, exp, log, ln, etc.). It should also provide a way to define custom
     mathematical functions.

DO28 (should)
     VHDL-A should support the description of piecewise defined behavior.

DO29 (should)
     VHDL-A should provide an integral operator. It must be at least defined
     from time zero to the current simulation time).

DO30 (should)
     VHDL-A should support the annotation of physical units to waveforms.

DO31 (desirable)
     It is desirable that VHDL-A support dimensional analysis.


---- Behavior description (DO18, DO19)

Another primary motivation for analog hardware description languages (AHDL) is 
to ease the user in creating models for new devices (for example, in VLSI 
circuits using the deep submicron technology), or developing simple behavior 
models for portion of complex circuits, or the environment of ASIC applications 
(for example, mechanical parts or thermal environment) in order to perform full 
system simulation. These models are best described by a set of linear/nonlinear 
differential/algebraic equations. A key feature of an AHDL is to provide the 
user the ability to describe these equations directly. A simulator is said to 
support an AHDL if it can simulate a circuit/system described in the AHDL 
syntax. This is often called behavior modeling capacity. Behavior modeling is a 
more general concept than commonly used ideal behavior modeling and 
transfer-function modeling. SPICE-like simulators does not support behavior 
modeling. In order to use SPICE-like simulators, one has to represent the 
behavior by a netlist of built-in primitive components. This is often called 
the macromodeling approach. Although macromodeling has been widely used before 
the advent of AHDL, it takes enormous effort, and often turns out impossible. 
The capacity of behavior modeling also makes it possible to simulate a behavior 
specification of a circuit/system to design, or a circuit/system with portions 
available as behavior specification. An example of behavior specification is by 
signal-flow diagrams or design equations.


---- Support of equations (DO18, DO19)

Equations are the natural way to describe behavior in analog systems. 
Mathematically, an equation describes a relation to be always satisfied between 
quantities. There are basically two forms of equations.

Implicit equations have the general form:

    F(Q1, Q2, ..., P1, P2, ..., V1, V2, ...) = 0

where Qi are quantities involved in the equation (unknowns), Pi are constant 
parameters, and Vi are the independent variables (e.g. time or frequency). As 
an example, here is the implicit equation binding two currents in a current 
mirror circuit:

    Ut * log (I/Iref) = -RI

The solution of implicit equations must be computed through iterations.

Explicit, or separable, equations have the general form:

    Q1 = G(Q2, Q3, ..., P1, P2, ..., V1, V2, ...)

where quantity Qi does not appear on the right-hand side of the equation. A 
very simple example of explicit equation is the ideal constitutive equation of 
a capacitor:

    i(t) = C * du(t)/dt

Providing the right-hand side of an explicit equation is known, the quantity on 
the left-hand side may be computed immediately.

Both implicit and explicit forms must be supported in VHDL-A, because both may 
naturally occur when describing analog behavior. While it is straightforward to 
transform an explicit equation into an implicit one, the other way around, i.e. 
implicit to explicit, is not always possible, or may lead to less 
understandable descriptions.

Conceptually, all equations are simultaneous and must be gathered into one set 
before simulation. The order in which equations are written in the description 
has no effect on the simulation results. Another, but related, aspect is to 
express analog behavior as a sequence of assignments where the order is 
important (procedural style). This might be required when some computation of 
equation parameters is needed. Also, explicit equations may be solved 
procedurally to accelerate the simulation.


---- Support of mixed behavioral and structural descriptions (DO20, DO21)

This design objective comes from a fundamental requirement that VHDL-A must 
support evolutionary design methodologies spanning the whole design process. 
For such design methodologies, it is often the case that a single design can 
contain, even with a single design entity, aspects that are structural in 
nature and others that are behavioral in nature. This kind of description tends 
to evolve naturally through the process of hierarchical design of a part: as 
the layers of the part are successively designed, more and more of the 
description may be given as a netlist of component instantiation; the remaining 
parts are still described as behavioral specification. On the other hand, 
during the bottom-up verification phase, it is a must that the behavior of leaf 
cells be described at the behavior level in order to simulate the entire 
system. Also, in order to do full-system verification, it is often required to 
model some part of the design directly at the behavior level. This ability is 
also desirable for simulation of mixed discipline systems where some part may 
have to be described at the behavior level.

There are several reason for supporting mixed structure and behavior 
description at a single design entity. First, VHDL¹93 allows the mixture of 
behavior and structure description for one single design entity, and so are 
some commercial HDLs. Second, the end users may want to perform some checking 
or statistics collection regarding a design described at the structural level. 
For example, interface timing checking for digital circuits, like ASSERTION, 
and power consumptions for analog circuits (more precisely analog abstraction, 
since the only approach to figure out the power consumption of a digital 
circuit is to use its analog abstraction and to do a detailed electrical 
simulation.). These checking tasks require the access of the behaviors of the 
systems described at the structural level. Third, under some circumstances, it 
may not be a good practice to represent a single design entity that some part 
is behavioral in nature and some part is structural in nature into two separate 
entities each containing either only behavioral description or only structural 
description. Finally, it is believed that this ability provides the user with 
more convenience.

Since both behavior and structure may be freely mixed in the same description, 
the behavior part may need to have access (read, write, or both read and write) 
to quantities that are used inside an analog component. The interface of an 
analog component usually defines connection points, or pins (i.e. terminals at 
which conservation laws are satisfied). However, abstract models may select to 
describe some coupling between behavior and structure which does not rely on 
conservation-law connection points. Controlled sources are a typical example: a 
current source in a design entity A with its current value controlled by the 
current of a voltage source in another design entity B. The current of the 
voltage source is a through quantity not associated with terminals of entity B. 
A convenient and natural way must be provided to the user for describing the 
voltage source, entity B, and entity A. In particular, it is not desirable to 
specify this voltage source as a three-terminal device. Note that the values 
involved in such coupling may change during the same simulation run.


---- Support of parametric models (DO22, DO23)

Parameters usually refers to those inputs to a model (circuit primitive) that 
are not related to its connection. For example, resistance value of a resistor, 
temperature for a transistor model. Such values are static, i.e. they are known 
before simulation and they are not allowed to change during one simulation run.
However, it may be possible that one model¹s parameters are through/across 
quantities of another model usually in different disciplines. For example, 
temperature of a transistor may be an across quantity in the thermal network 
used to model the thermal environment of the transistor. Such parameters will 
automatically change during simulation. A special case is parameters that 
depend on independent variable of an analysis. For example, time-dependent 
resistance in transient analysis, and frequency-dependent capacitance in 
frequency analysis. This means that the independent variable should be 
available to the model.

There are several requirements in order to support parametric models: First, 
parameters can be default. Second, parameters can be deliberately left 
unspecified. In that case, they act as flags to indicate that some additional 
work is to be performed. A typical example is the preprocessing of MOS model 
parameters. Third, parameters may be analysis specific or generally applicable. 
Fourth, parameters may be not necessarily coefficients for equations or 
condition variables. They may be those used to create coefficients for 
equations or condition variables. The ability of value or range checking must 
be supported.


---- Support of discontinuous behavior (DO24, DO28)

Switched-capacitor circuits are a typical example where the analog behavior is 
discontinuous. Also, at higher levels of abstraction, the behavioral modelling 
of a bouncing ball or of stick/slip friction are typical examples. In these 
cases, the model might require explicitly the simulator to compute the state of 
the system at a specific point in time (or frequency), or it might specifiy the 
new values some quantities (and their derivatives) will have just after the 
discontinuity. The conditional switch between equations must also be supported 
in VHDL-A. An analog behavior may depend on some operating conditions which may 
change during simulation.

Another kind of discontinuous behavior is the explicit specification of 
discontinuous input stimuli, e.g. piece-wise linear input sources. It is usual 
in SPICE-like simulator to take the breakpoints into account during simulation 
by forcing an evaluation of the state of the circuit when the break occurs in 
time. This does not, however, affect how the model is written, but rather how 
accurately the simulator will compute the output waveforms. The issue here is 
to decide whether or not the new canonical mixed-mode simulation cycle in 
VHDL-A will explicitly say what to do in this case.

Yet another aspect that requires the support of discontinuous behavior is mixed 
digital-analog description and simulation. It will be discussed later in this 
document.


---- Standard operators and functions (DO26, DO27, DO29)

The time derivative operator is an essential means for describing differential 
equations for dynamic (time-dependent) analog systems. In addition, 
theoretically, all derivatives other than time derivatives can be expressed by 
using time derivatives, although numerical inaccuracy may occur in that case. 
Derivatives w.r.t. other variables/quantities than the time are for example 
useful for device modelling, because it is not always possible to write 
analytical expressions. Following the preceding discussion about SPICE 
compatibility, it should not be very limitating if only derivatives w.r.t. time 
are supported in VHDL-A.

The integral operator is needed for the matter of convenience. Every expression 
that involves an integral may be easily transformed into another one that uses 
a derivative. The integral operator must be defined from time zero to the 
current simulation time, which we know how to handle.

In order to describe a system, certain mathematical tools and abilities must be 
provided. All standard functions provided in a scientific (or engineering) 
language like C should be available in a math library for the user convenience. 
Such functions should not require the VHDL'93 "foreign" mechanism, since there 
will be a standard mathematical package for VHDL soon. The only additional 
requirement VHDL-A is asking for is to allow the future standard mathematical 
functions to operate on double precision floating values. Other functions like 
NAG or IMSL are outside of the scope of VHDL-A, but anybody who needs these 
functions can write a package and call them using VHDL'93 "foreign" mechanism. 
It may also be useful for a user to define their own functions, or to overload 
existing ones with proprietary implementations.


---- Support of physical units and dimensions (DO30, DO31)

All physical quantities are associated with units of measurement. There are 
seven basic units: meter, kilogram, second, ampere, kelvin, candela, and mole, 
which are defined by the standard ISO-1000, called SI units. All other units 
can be expressed in terms of these seven basic units.

VHDL-A must support the ability of manipulating a physical quantity together 
with its related units. This is needed for documentation purposes and for 
interpreting the simulation results. It is a very useful feature especially in 
case of mixed discipline systems.

Further, it is very desirable that any assignment operation or equation 
formulation be checked for dimensional equivalence. Equivalence checking is a 
more involved process, which requires defining and applying rules that specify 
how dimensioned quantities are arithmetically combined and how basic units are 
combined to express in terms of non-basic units (for example, use the watt as 
the unit of power).

Full dimensional analysis in VHDL-A is only considered as desirable, that is as 
a feature which would increase the user¹s convenience, although not primarily 
needed as a basic functionality. On the other hand, the annotation of 
quantities with physical units is almost straightforward to include in VHDL-A. 
Care must be taken however not to affect the future implementation of 
dimensional analysis.


6. Simulation mechanisms
------------------------

This section is devoted to design objectives that are targeted for simulation 
specific issues. There are three fundamental reasons for these design 
objectives. First, VHDL, which is a basis of VHDL-A, defines a canonical 
simulation cycle. In order to be compatible with VHDL, VHDL-A must define its 
simulation mechanism that degenerates to the canonical simulation cycle of VHDL 
for pure digital systems. Second, the scope of VHDL-A is to support the 
simulation of mixed digital and analog systems. Therefore, the interaction 
between digital simulation and the analog simulation, has to be specified. 
Finally, analog simulation (and analysis) itself requires certain parameters to 
be specified. For example, the convergence tolerance for the Newton-Raphson 
algorithm. However, these parameters depend not only on specific analog 
analysis, but also on the specific algorithm, and even on specific 
implementation of the algorithm in a specific tool.


DO37 (must)
     Compliance with VHDL-A must not depend on the specification of an
     underlying simulation algorithm for the analog kernel.

DO38 (must)
     VHDL-A must define the mechanism related to the simulation of the analog
     part of a VHDL-A description as well as the mechanism related to the 
     simulation of mixed digital-analog descriptions.

DO39 (must)
     VHDL-A must support the specification of user-defined initial conditions.
     It must also provide a way to start the simulation in a consistent state.

DO25 (must)
     The maximum simulation time for a mixed analog/digital system must not be
     restricted by the minimum time resolution of VHDL'93.

DO40 (should)
     A communication mechanism should be provided to pass information back and
     forth between the VHDL-A model and the analog simulation kernel. Only the
     communication mechanism should be defined, not the way the simulator will
     handle them.


---- Support of analog simulation and mixed analog-digital simulation
     (DO37, DO38)

For a digital system, the specification of its behavior and the structure in 
VHDL also defines uniquely the simulation algorithm. Analog description is only 
denotational, which only specifies the set of equations that the system must 
satisfy. There are many algorithms for solving the set of equations and finding 
the behavior of the system. Each has its advantage for simulating certain 
circuits/systems under certain design styles and targeted technologies. 
Practically, depending on the needs, one may want to use a very accurate, but 
expensive (time and memory consuming), or a simplified, but fast, simulation 
algorithm. VHDL-A, targeted as a language standard, must be technology 
independent and methodology independent. Therefore, no specific algorithm can 
be defined, or included in the new mixed digital-analog canonical simulation 
cycle. In fact, this design objective leads to one of the most challenging 
aspects of VHDL-A design.

On the other hand, we need to support mixed simulation. Therefore, VHDL-A must 
provide a mechanism related to mixed analog and digital simulation. Ideally, we 
would like to have an abstract model that has two essential features: one is to 
serve as a common abstraction of all analog simulators, and the other is for 
the integration with digital simulation, i.e., time synchronization. These 
aspects are very important to ensure a reasonable degree of portability for the 
models written in VHDL-A.

Mechanisms to support mixed analog and digital simulation, in particular, the 
interaction between analog and digital simulation kernels, is perhaps the most 
critical but least known aspect of VHDL-A. From the analog description and 
simulation point of view, this is a language design even simulator development 
issue. However, digital behavior specification also defines how it simulates. 
For the sake of compatibility and to support mixed simulation, the interaction 
between the two simulation kernels is a design objective issue.


---- Initialization of analog simulation (DO39)

Initialization is a part of the digital canonical simulation cycle in VHDL¹93. 
Initialization of digital part of a mixed digital and analog system requires 
the initial states of analog part to be known. Therefore for both the 
compatibility and functionality, VHDL-A should define explicitly the 
initialization of analog part. However, analog initialization is a much more 
complicated process than digital initialization.

In VHDL¹93,  initialization is the first step in the canonical simulation 
cycle. It mainly assigns initial values to all signals and variables in the 
description and runs each process once until it suspends. A digital model is 
therefore in an inconsistent state after initialization. This means that the 
values the signals have at this point may not reflect the real state of the 
model. This does not, however, bring problems for the simulation, because the 
correct state of the model should be reached after a few simulation cycles. 
Consistency would only be reached if the processes were executed repeatedly 
until the event queue is empty, while at the same time the stimuli are frozen 
(i.e. does not create any new events).

Analog initialization, on the other hand, involves the formulation of system 
equations and the solution of the formulation in order to find an initial state 
(DC operating point computation). It is commonly accepted that the formulation 
of system equations and its solution is beyond the scope of VHDL-A. So what we 
can probably define as a design objective is that VHDL-A must support the 
specification of initial conditions. A DC analysis is another, specific, kind 
of analysis which may be required to get a consistent state before time-domain 
or small-signal AC analysis.

One concern in the specification of initial conditions is how to handle 
inconsistent initial conditions. In addition, there are two other concepts 
related to initial conditions, which may need to be considered altogether 
during language design. The first one is starting point of iterative algorithms 
for solving nonlinear equations. For some analog simulators, initial conditions 
are also used as the starting point for numerical solution algorithms. The 
other concept is that, for certain analog systems that have multiple DC states 
(solutions), some information about the initial state must be provided in order 
to find a unique solution.


---- Simulation time limitation (DO25)

This objective addresses a problem that may occur during the simulation of 
mixed digital-analog models. If analog and digital kernels are synchronized 
with the VHDL'93 minimum resolvable time (MRT) of 1fs, the maximum simulation 
time of a mixed system is restricted to about 9s if the time is implemented as 
a double precision variable (53 bits of resolution => 2**53 * 1fs maximum 
time). This is clearly insufficient for some system applications where the time 
constants may easily be in the order of seconds (e.g. if a motor is involved). 
VHDL already provides a workaround to this problem by allowing to select a 
secondary unit of time as the MRT which is larger than 1fs, at the price of a 
reduction of accuracy however. VHDL-A must also support this feature at the A/D 
interfaces of the model.

For pure analog models,simulation time limitation should not be a problem 
providing analog time is based on real values, not integer values as for 
digital ones. Moreover, the problem of stiff systems, i.e. analog systems 
exhibiting time constants of different order of magnitude, is usually solved in 
the simulator by using appropriate numerical integration methods (e.g. Gear 
methods). This does not have any impact on the VHDL-A language as such.


---- Simulation control (DO40)

Simulation control is needed in some form because analog simulation methods may 
use various numerical algorithms. The accuracy of the solution is usually 
related to a set of numerical tolerances, in order to decide whether the 
solution has converged or not, and also to the actual implementation of the 
numerical algorithms, because they are optimized towards this specific usage 
(e.g. limiting schemes to avoid numerical overflow).

Another point related to simulation control is to allow VHDL-A to perform 
statistical simulations, where the same model is simulated several times for 
different values of some specific parameters.


7. Interactions between analog and digital
------------------------------------------

Simulation of mixed analog and digital systems requires three aspects of 
analog/digital interactions to be specified as design objectives. One is the 
dynamic communication between the two different simulation kernels that handle 
respectively analog and digital abstractions. This has been described in the 
previous section. The other two aspects are rather static, concerning the 
conversion between digital signal and analog waveform (behavior), and the 
conversion between digital connection point and analog connection point 
(structure). In fact, the interaction between simulation kernels is embodied 
through the conversion between analog and digital abstractions.


DO32 (should)
     Default conversions between analog and digital connection points should be
     provided.

DO33 (must)
     A system-supplied thresholding function must be accessible to the user in
     defining customized thresholding functions. The user must be able to
     define what a "significant change" is that defines thresholds within the
     analog system.

DO34 (must)
     VHDL-A must support at least the following analog to digital interaction
     mechanisms:
     - a digital process must be able to read an analog value
     - it must be possible to make a digital process sensitive to an analog
       value.

DO35 (must)
     VHDL-A must support at least the following digital to analog interaction
     mechanisms:
     - an analog behavioral model must be able to read a digital signal
     - it must be possible to make an analog behavioral model sensitive to a
       digital signal. In particular, it must be possible to enforce an analog
       time step in response to an event on a digital signal.

DO36 (should)
     VHDL-A should  provide a mechanism to handle the intrinsic instantaneous
     change of digital signal values that affects the behavior of analog part.


---- Default conversions between analog and digital structures (DO32)

Due to the strong typing mechanism of VHDL, it would not be allowed to directly 
connect a VHDL signal to a VHDL-A pin, or a VHDL-A node to a VHDL port. Also, 
it is not in the VHDL philosophy to define default conversion functions to 
allow to connect two ports of different types. Type casting is moreover limited 
to a few cases. However, there are cases in where an analog-digital interface 
is only needed because one wants to simulate parts of a system at different 
abstraction levels. For example, when the real system will work as a digital 
system, but some detailed, critical, timing informations are needed to validate 
its global behavior. In that case, there won¹t be any real A/D or D/A converter 
in the final system, but simulation needs some conversion to proceed. The 
objective here, which is not a primary one, is just to avoid to force the user 
to describe explicit conversion statements whenever they do not correspond to 
real functionality in the designed system.


---- Analog to digital interactions (DO33, DO34)

Analog to digital interaction involves the transformation of an analog 
waveform, which is continuous in amplitude and in time, into a digital signal, 
which is quantized in amplitude and discrete in time. Therefore both a value 
conversion and a time conversion are to be performed.

For data value conversion, a threshold function is usually used to convert an 
analog waveform to a digital signal. For an electronic system, the voltage of 
the analog connection point would be transformed into a legal digital value in 
the logic value system in use. The current of the analog connection point may 
also be used to get a more specific digital value when multivalued logic is 
used (such as the IEEE 1164 standard 9-state LVS). From the analog side, the 
analog part should see a load (e.g. a stray capacitance) that models the fact 
that it is connected to something and not left open. For time value conversion, 
the real based analog time has to be rounded or truncated to the nearest 
multiple of the digital integer based time.

What the threshold is must be customizable by the user, but the mechanism to 
specify that the digital part is waiting for some event from the analog part, 
along with how the simulation should react to that event, must be precisely 
defined in VHDL-A.


---- Digital to analog interaction (DO35, DO36)

Digital to analog interaction involves the transformation of a digital signal 
into an analog waveform. It also requires a value conversion and a time 
conversion.

For data value conversion, the value of the digital signal has to be translated 
into both across and through values in the analog part. For electronic systems, 
a specific voltage-controlled switch might be used. Depending on the signal 
value, the switch selects one of several identical subcircuits (usually a 
non-ideal voltage source with a parallel capacitor), but with different 
component values, to act as an input component for the analog part. The number 
of input subcircuits depends on the number of states the digital signal may 
take. From the digital part, the fact that it is not open but connected to 
something might be modelled as a specific assignment delay for the signal going 
out the digital port. For the time value conversion, the integer based digital 
value is merely converted into its equivalent floating representation.

An important aspect is the discontinuities a digital signal will produce on an 
analog waveform. The instantaneous change of a digital signals value is likely 
to produce numerical difficulties when computing the state of the analog part 
in reaction to this change. Some "smoothing" function should be defined to 
avoid this. At least, a piece-wise linear "analog delay" should be produced on 
the analog waveforms at the D/A interface. More complex behaviors are also 
possible, such as an exponential change between to analog values.


8. Concluding remarks
---------------------

In this document, the complete set of design objectives for the design of the 
VHDL-A language have been given and discussed. All the related work has been 
done, and is currently going on, within the IEEE 1076.1 working group whose 
goal is to propose a consistent set of extensions that supports the description 
and the simulation of analog and mixed analog-digital hardware systems. Based 
on the design objectives, a global architecture for VHDL-A is soon to be 
completed. It will contain precise definitions of all the new concepts VHDL-A 
is bringing to VHDL and will ensure that the VHDL philosophy is not violated. 
This last point is undoubtedly a strong constraint that limits the space of 
possible implementations. Nevertheless, the constraint might be a advantage 
since VHDL-A is evolving from VHDL, a standard and successful HDL.