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Chapter assignments for LRM 2.3

The Verilog-AMS committee is presently updating the Language Reference Manual to version 2.3. Many of the changes involve updating references to the underlying digital standard, IEEE Std. 1364-2005; previous versions of the AMS LRM were based on 1364-1995.

Below is a list of the chapters and appendices of the LRM and the committee members who have agreed to update the text of those chapters. If a draft update was produced, the chapter title is a link to the latest version.

Chapter Assignee Last reviewed
1. Introduction none n/a
2. Lexical Conventions Graham Helwig, ASTC 30 May 2006
3. Datatypes Geoffrey Coram, Analog Devices 6 Sept 2007
4. Expressions Dave Miller, Freescale 30 Aug 2007
5. Signals Geoffrey Coram, Analog Devices 11 Apr 2006
6. Analog Behavior Sri Chandra, Freescale 30 Aug 2006
7. Hierarchical Structures Arpad Muranyi, Intel
Marq Kohl, NXP
11 Jan 2007
8. Mixed Signal Dave Miller, Freescale 23 Jul 2007
9. Scheduling Semantics Junwei Hou, Cadence n/a
10. Sys Tasks & Functions Martin O'Leary, Cadence
(Patrick O'Halloran, Tiburon for $table_model)
30 Aug 2007
11. Compiler Directives Graham Helwig, Freescale 16 Aug 2007
12. Using VPI none n/a
13. VPI Definitions none n/a
Annex Assignee Last reviewed
A. Syntax Graham Helwig, Freescale ongoing
B. Keywords none n/a
C. Analog subset Marq Kole, NXP n/a
D. Standard definitions Geoffrey Coram, Analog Devices
Martin O'Leary, Cadence
19 Oct 2006
E. Spice compatibility Marq Kole, NXP 6 Sept 2007
F. Discipline resolution none n/a
G. Open issues none n/a
H. Glossary none n/a

   Last updated on
   Sept. 7, 2007