IEEE SystemVerilog WG
News:
The IEEE SA Board has approved a new PAR. Elections have been held and new officers for the Working Group have been elected. The next meeting is a teleconference on 8 November 2006.
Scope:
SystemVerilog is a Unified Hardware Design,
Specification and Verification language that is based on the
work done by Accellera, a consortium of Electronic Design
Automation (EDA), semiconductor, and system companies.
The proposed project will create an IEEE standard that is
leverage from Accellera SystemVerilog 3.1a. The new
standard will include design specification methods, embedded
assertions language, test bench language including coverage
and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity
boost in design and validation, and covers design, simulating,
validation, and formal assertions based verification flows.
Purpose:
The purpose of this project is to provide the EDA,
Semiconductor, and System Design communities with a
well-defined and official IEEE Unified Hardware Design,
Specification and Verification standard language. The
language is design to co-exist and enhance those hardware
description language is designed to co-exist and enhance those
hardware description languages presently used by designers
while providing the capabilities lacking in those languages.
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Announcements
Related
Web Sites
LRMs:
Accellera SystemVerilog 3.1a LRM
Current Drafts:
Password Protected
There are no drafts. The standards are approved and available from the IEEE.
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