VHDL Synthesis Interoperability Working Group
IEEE PAR 1076.6
Meetings

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Upcomming Meetings:
The next VHDL Synthesis Interoperability Working Group meetings are scheduled for:

  • Thursday, June 18, '98, 9:00am to 12:00pm at Mentor Graphics, in San Jose

    • All meetings will be full-day meetings. Please plan accordingly.

    Notes from SIWG meetings:

  • Apurva's presentation on hardware inference. Last Updated 11/7/96
  • Rough draft of the recommendations for pragmas/metacomments/preprocessor directives Last Updated 9/9/96

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    Last modified: Tue Jun 9 12:15:33 EDT 1998

    Please send feedback to David Bishop dbishop@vhdl.org