//---------------------------------------------------------------------------
//
//       ASSERT_NEVER_AT_X_OR_Z
//
//---------------------------------------------------------------------------
// NAME
//          ASSERT_NEVER_AT_X_OR_Z - An invariant concurrent assertion to 
//                                   ensure that no bits of a variable are 
//                                   at X or Z (sampled at each clock edge)
//
//---------------------------------------------------------------------------
module assert_never_at_x_or_z (clk, reset_n, qualifier, test_expr);
// synopsys template
   parameter severity_level = 0;
   parameter width=1;
   parameter msg="VIOLATION";
   input     clk, reset_n;
   input     qualifier; // set to 1'b1 if not required
   input [width-1:0] test_expr;
 
`ifdef ASSERT_ON
  `ifdef ASSERT_OVL_VERILOG
  `else
    `define ASSERT_OVL_VERILOG
  `endif
`endif
  
//synopsys translate_off
`ifdef ASSERT_OVL_VERILOG

  parameter assert_name = "ASSERT_NEVER_AT_X_OR_Z";

  integer error_count;
  initial error_count = 0;

  `include "ovl_task.h"

  `ifdef ASSERT_INIT_MSG
    initial
      ovl_init_msg; // Call the User Defined Init Message Routine
  `endif

  always @(posedge clk) begin
    `ifdef ASSERT_GLOBAL_RESET
      if (`ASSERT_GLOBAL_RESET != 1'b0) begin
    `else      
      if (reset_n != 1'b0) begin
    `endif
        if (qualifier) // no error if qualifier is X
           if ((|(test_expr ^ test_expr)) == 1'b0) // can only be 1'b0 or 1'bx
              begin
                 // NOP - signal contains no X or Z
              end
           else
              ovl_error("");
      end // if (<reset>)
   end // always

`endif
//synopsys translate_on

endmodule