The OVL provides designers, integrators, and verification engineers with a single, vendor- and language-independent template interface for design validation. However, the OVL is actually a library of predefined assertions, not a temporal property or assertion language (such as PSL or SVA). In reality, the OVL is a library-based assertion methodology that lets the engineer use the same assertion specification with different languages (which means good tool support across different flows) and in different parts of the design flow (for example, RTL simulation, formal proof, emulation, and FPGA prototyping). A designer can start adding assertions quickly (without taking on an appreciable learning curve or making mistakes in a language) and be confident that the pre-defined assertions in OVL have undergone considerable testing.

While standardizing property and assertion languages is integral to addressing increased verification complexity, it is not the entire solution. Equally important to the ABV revolution is an effective methodology that unifies traditional and formal verification within an ABV framework. The new Accellera OVL provides a systematic element of an ABV methodology. For example, the OVL incorporates a consistent and systematic means of specifying RT-level implementation properties structurally through a common set of library elements (that is, assertion monitors). The OVL library elements act like a template that lets designers express a broad class of assertions in a common, familiar RTL format. Furthermore, the OVL capitalizes on the various emerging property and assertion language standards by unifying the PSL declarative form of property specification with the new SystemVerilog procedural form of specification within the library. In addition, these library elements address assertion-based methodology considerations by encapsulating a unified and systematic method of reporting that can be customized per project and a common mechanism for enabling and disabling assertions during the verification process. The reporting and enable/disable features use a consistent process that enforces uniformity and predictability in a project's assertion-based methodology. Finally, the new Accellera OVL was extended to provide an automatic means to measure coverage that enables verification teams to improve the efficacy of the test environment.

Fundamental to understanding the benefits of assertions in general and OVL assertions in particular, is an understanding of the concepts of controllability and observability:

  Controllability  The ability to stimulate all parts of the design under test
  Observability  The ability to propagate the effects of a bug to an observable point

In general, assertions help solve the observability challenge in simulation, but they do not help with the controllability challenge. However, by adopting an assertion-based, constraint-driven simulation environment, or applying formal property checking techniques to the design assertions, we are able to address the controllability challenge. Furthermore, by including coverage measurements directly in an assertion module (such as the OVL), the verification environment can report valuable information back to the users, thus helping them uncover holes in input stimulus and missing scenarios, (for example, cases where the stimulus never activated a triggering condition for a particular assertion).