- What is OVL? A library of pre-defined assertions, implemented in several languages (currently Verilog, SVA, and PSL)
- Where can I get OVL? From the Downloads area.
- Why not use PSL/SVA directly? Property languages have advantages, but so do assertion libraries. OVL assertions are easy to understand and use, are well tested and have built-in functional coverage. OVLs can also be reused across methodologies: modelling, RTL simulation/formal, synthesis (including FPGA prototyping & verification). Being able to link to different languages also means that you get the best of both worlds e.g. fast simulation regressions with Verilog but good debug in SVA.
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