This section contains a number of simple examples as tutorial material for getting started with OVL.

Slides for these examples can be found here: Documentation for OVL Examples

This is a simple state machine example, the Test Access Port (TAP) specified in the IEEE 1149.1 standard. The standard itself mentions a synchronous-reset property that can easily be specified with an OVL assertion.

Verilog source for this example can be found here: TAP Controller (verilog)

This example contains several assertions along with a number of different designs that have evolved to meet all the requirements. This is a good example of Assertion Based Design. The OVL assertions are written in both Verilog and SVA flavours for this example.

Verilog source for the arbiter OVLs can be found here: Arbiter (Verilog OVL)

SVA source for the arbiter OVLs can be found here: Arbiter (SVA OVL)

Complete source (design + OVL) for this example can be found here: Arbiter (RTL + SVA/Verilog OVL)