Examples
E.1 access types:
PROCESS ...
TYPE twobits IS ARRAY (0 TO 1) OF BIT;
TYPE twobits_pointer_type IS ACCESS twobits; -- declare an ACCESS type.
-- The subprograms NEW and DEALLOCATE are declared implicitly
VARIABLE p1, p2 : twobits_pointer_type; -- declare two pointer variables
...
BEGIN
...
p1 := NEW twobits; -- allocate memory for an object of type "twobits"
p1.ALL := ('0','1'); -- store a value to the memory location
p1.ALL(0) := p1.ALL(1); -- referencing subelements of an array pointed by
-- an access value
p1(0) := p1(1); -- same as "p1.ALL(0) := p1.ALL(1)"
p2 := p1; -- "p2" and "p1" are now pointing to the same memory location
DEALLOCATE(p2); -- free memory
p1 := NULL; -- "p1" now points to nil
END PROCESS;
E.2 array and record aggregates:
SIGNAL bvec : BIT_VECTOR(0 TO 3);
SIGNAL one_bit : BIT_VECTOR(0 TO 0);
SIGNAL b1, b2, b3, b4 : BIT;
TYPE rec IS RECORD
a : BIT;
b : INTEGER;
END RECORD;
SIGNAL rvec : rec;
...
-- examples for array aggregates
bvec <= (1=>'1', OTHERS=>'0'); -- assigns ('0','1','0','0') to "bvec" (named
-- association)
bvec <= ('0','1','0','0'); -- positional association
(b1,b2,b3,b4) <= bvec AFTER 20 ns; -- "b1" will be assigned "bvec(0)",
-- "b2" "bvec(1)", ...
one_bit <= (0=>'1'); -- named association has to be used to create an
-- aggregat containing only a single element
-- examples for record aggregates
rec <= ('0', -9); -- "rec.a" = '0', "rec.b" = -9 (positional association)
rec <= (b=>123, a=>'1'); -- "rec.a" = '1', "rec.b" = 123 (named association)
E.3 array and record types:
-- constrained arrays
TYPE word IS ARRAY (31 DOWNTO 0) OF BIT;
TYPE memory IS ARRAY (0 TO 100, 0 TO 7) OF BIT; -- two dimensional array
-- unconstrained arrays
TYPE r_vector IS ARRAY (POSITIVE RANGE <>) OF REAL;
TYPE i_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; -- POSITIVE and NATURAL
-- are predefined integer subtypes ranging 1 to INTEGER'HIGH,
-- respectively 0 to INTEGER'HIGH
...
-- declaring array objects
VARIABLE bus : word := (OTHERS => '0'); -- default value of bus
-- is ('0','0',...'0')
VARIABLE mem : memory := (OTHERS => (OTHERS => '1')); -- default value of mem
-- is (('1',...'1'),...,('1',...'1'))
VARIABLE a : r_vector(1 TO 3) := (1.0, 2.4, 3.4); -- "a" has 3 elements
VARIABLE b : i_vector(0 TO 1); -- "b" has two elements
...
-- accessing array elements
bus(3) := mem(2,3);
-- record types
TYPE rec IS RECORD -- record type "rec" contains 4 elements "a" to "d"
a : BIT;
b : INTEGER;
c : REAL;
d : bit_vector(0 TO 2);
END RECORD;
-- declaring record objects
VARIABLE rec_var : rec := ('0', 34, -123.4, (OTHERS => '0')); -- "a" = '0',
-- "b" = 34, "c" = -123.4 and "d" = ('0','0','0')
-- accessing record objects
rec_var := (a=>'1', d=>('0','1','0'), b=>-1, c=>12.45);
rec_var.a := '0'; -- accessing element "a" of record "rec_var"
rec_var.b := 111; -- accessing element "b" of record "rec_var"
E.4 assertion statement:
VARIABLE a,b : INTEGER;
...
a:= 10;
b:= 11;
-- the assertion statement will report a message only if the condition
-- expression evaluates to FALSE
ASSERT a /= b -- assert statement will report nothing because
REPORT "a not equal b" -- a /= b evaluates to TRUE
SEVERITY WARNING;
ASSERT a = b -- assert statement will report the WARNING
REPORT "a not equal b" -- message "a not equal b"
SEVERITY WARNING;
ASSERT a = b
REPORT "a not equal b"; -- will report the ERROR message "a not equal b"
ASSERT a = b; -- will report the ERROR message
-- "Assertion violation"
E.5 attributes:
TYPE int_up IS INTEGER 0 TO 100;
TYPE int_down IS INTEGER 99 TO -1;
TYPE vec IS ARRAY (3 DOWNTO -1) OF INTEGER;
TYPE vec2d IS ARRAY (0 TO 3, 5 DOWNTO 1) OF BIT;
VARIABLE bus : vec;
-- examples for some predefined attributes
a := int_up'LEFT; -- a = 0
a := int_up'LOW; -- a = 0
a := int_up'HIGH; -- a = 100
a := int_down'LEFT; -- a = 99
a := int_down'HIGH; -- a = 99
a := vec'LEFT; -- a = 3; note: "vec" is an array type
a := bus'RIGHT; -- a = -1; note: "bus" is an array object
a := bus'LOW; -- a = -1
a := vec2d'LENGTH(1); -- a = 4, size of the first dimension of "vec2d"
a := vec2d'HIGH(2); -- a = 5
E.6 base type:
TYPE vec IS ARRAY (3 DOWNTO -1) OF INTEGER; -- the base type of type
-- "vec" is "vec"
SUBTYPE memory IS bit_vector(1 TO 100); -- the base type of "memory" is
-- "bit_vector"
SUBTYPE pin_count IS INTEGER 1 TO 20; -- the base type of "pin_count"
-- is "INTEGER"
E.7 bit strings:
B"0110_1001"; -- (binary), length is 8, equivalent to
-- ('0','1','1','0','1','0','0','1')
B"0110100110"; -- (binary), length is 10, equivalent to
-- B"01_1010_0110"
X"65"; -- (hexadecimal), length is 8, equivalent to
-- B"0110_0101"
O"126"; -- (octal), length is 9, equivalent to
-- B"001_010_110"
E.8 internal block:
ARCHITECTURE block_struct OF test IS
SIGNAL clock : BIT := '0';
SIGNAL count : INTEGER := -1;
...
BEGIN
alu: BLOCK
PORT (clk IN BIT; counter : INOUT INTEGER); -- interface of block alu
PORT MAP(clk => clock, counter => count); -- port map association list
... -- declarations for "alu"
BEGIN
counter <= counter + 1;
...
END BLOCK alu;
...
END block_struct;
E.9 concurrent statements:
ARCHITECTURE concurrent OF test IS
SIGNAL sig, data, dum : BIT;
PROCEDURE test_proc (val1 : IN BIT; pdata : IN BIT) IS
BEGIN
...
END test_proc;
BEGIN
-- concurrent signal assignment
alab1: -- label
sig <= '1' AFTER 10 ns, '0' AFTER 15 ns; -- INERTIAL delay
data <= TRANSPORT '1' AFTER 20 ns; -- TRANSPORT delay
data <= REJECT 5 ns INERTIAL '1' AFTER 10 ns, '0' AFTER 15 ns; -- same as
-- INERTIAL delay, but only spikes with a pulse width less
-- than 5 ns are deleted. NOTE: you must have a VHDL'93
-- compliant compiler/simulator to use "REJECT"
-- conditional signal assignment
dum <= '1' AFTER 10 ns, '0' AFTER 15 ns WHEN data_i = 100 ELSE
'1' AFTER 20 ns WHEN data_i = 100 AND data_i = 99 AND sig = '0' ELSE
'0' AFTER 100 ns;
-- selected signal assignment
WITH data_i SELECT
'1' AFTER 10 ns, '0' AFTER 15 ns WHEN 1 | 10 , -- assign waveform if
-- "data_i" = 1 or "data_i" = 10
'1' AFTER 20 ns WHEN 100,
'0' AFTER 2 ns WHEN OTHERS; -- default assignment
-- process statement
pname1: PROCESS
VARIABLE count : INTEGER := 0;
BEGIN
COUNT := COUNT + 1;
...
WAIT ON data;
END PROCESS;
-- concurrent assertion statement
ASSERT dum = '1'
REPORT "signal dum is '0'"
SEVERITY WARNING;
-- concurrent procedure call
test_proc (val1=>sig, pdata=>data);
END concurrent;
E.10 default expression:
ENTITY test IS
GENERIC (def_val : BIT := '1'); -- default value of "def_val" is '1'
PORT (clk : IN BIT := '0'; data : INOUT BIT := def_val); -- default value
-- of "clk" is '0', the default value of "data" is "def_val".
-- Note, "def_val" is declared in the generic clause above!
END test;
ARCHITECTURE block_struct OF test IS
SIGNAL clock, reset_pin : BIT := '0';
SIGNAL count : INTEGER := -1;
SIGNAL bus : bit_vector(0 TO 7) := (4=>'1', OTHERS=>'0'); -- default value
-- of "bus" is B"0000_1000"
...
BEGIN
...
END block_struct;
E.11 deferred constant:
PACKAGE pack IS
CONSTANT c_normal : INTEGER := 100; -- normal constant
CONSTANT c_deffered : INTEGER; -- deferred constant
END pack;
PACKAGE BODY pack IS
CONSTANT c_deffered : INTEGER := -99; -- full declaration of constant
-- "c_deffered"
END pack;
E.12 incomplete type declaration:
-- example of a recursive type
TYPE mytype; -- incomplete type declaration
TYPE link_mytpe IS ACCESS mytype; -- define an access type for "mytype"
TYPE mytpye IS RECORD
next : link_mytype;
data : INTEGER;
END RECORD;
E.13 enumeration type:
TYPE colour IS (red, yellow, green);
TYPE four_state IS ('0', 'L', 'Z' 'X');
E.14 integer type:
TYPE state IS RANGE 0 TO 32;
TYPE bit_index IS RANGE 31 DOWNTO 0;
E.15 inertial delay:
SIGNAL data : INTEGER;
-- assume the actual projected output waveform of signal "data" is
-- (4, 8 ns) (12, 10 ns) (-1, 15 ns) (12, 18 ns) (100, 25 ns),
-- | |
-- | time
-- value
-- then the driver list after executing
data <= 12 AFTER 11 ns, 100 AFTER 15 ns;
-- at simulation time 3 ns evaluates to
-- (12, 10 ns) (12, 14 ns = 3 ns + 11 ns) (100, 18 ns)
E.16 transport delay:
SIGNAL data : INTEGER;
-- assume the actual projected output waveform of signal "data" is
-- (4, 8 ns) (12, 10 ns) (-1, 15 ns) (12, 18 ns) (100, 25 ns),
-- | |
-- | time
-- value
-- then the driver list after executing
data <= TRANSPORT 12 AFTER 11 ns, 100 AFTER 15 ns;
-- at simulation time 3 ns evaluates to
-- (4, 8 ns) (12, 10 ns) (12, 14 ns = 3 ns + 11 ns) (100, 18 ns)